mirror of
https://github.com/intel/isa-l.git
synced 2024-12-12 17:33:50 +01:00
1c71f9c0ae
Tweak performances with prefetch instructions. Below is the test results: - Neoverse N1: ~30% - Cortex-A72: ~3% - Cortex-A57: ~90% - Others: 50% - 5x Change-Id: I3ab292a953043dbaea98af3c66778f57da3a1331 Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>
58 lines
2.6 KiB
Makefile
58 lines
2.6 KiB
Makefile
########################################################################
|
|
# Copyright(c) 2020 Arm Corporation All rights reserved.
|
|
#
|
|
# Redistribution and use in source and binary forms, with or without
|
|
# modification, are permitted provided that the following conditions
|
|
# are met:
|
|
# * Redistributions of source code must retain the above copyright
|
|
# notice, this list of conditions and the following disclaimer.
|
|
# * Redistributions in binary form must reproduce the above copyright
|
|
# notice, this list of conditions and the following disclaimer in
|
|
# the documentation and/or other materials provided with the
|
|
# distribution.
|
|
# * Neither the name of Arm Corporation nor the names of its
|
|
# contributors may be used to endorse or promote products derived
|
|
# from this software without specific prior written permission.
|
|
#
|
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
#########################################################################
|
|
|
|
lsrc_aarch64 += \
|
|
crc/aarch64/crc_multibinary_arm.S \
|
|
crc/aarch64/crc_aarch64_dispatcher.c
|
|
|
|
lsrc_aarch64 += \
|
|
crc/aarch64/crc16_t10dif_pmull.S \
|
|
crc/aarch64/crc16_t10dif_copy_pmull.S \
|
|
crc/aarch64/crc32_ieee_norm_pmull.S \
|
|
crc/aarch64/crc64_ecma_refl_pmull.S \
|
|
crc/aarch64/crc64_ecma_norm_pmull.S \
|
|
crc/aarch64/crc64_iso_refl_pmull.S \
|
|
crc/aarch64/crc64_iso_norm_pmull.S \
|
|
crc/aarch64/crc64_jones_refl_pmull.S \
|
|
crc/aarch64/crc64_jones_norm_pmull.S
|
|
|
|
#CRC32/CRC32C for micro-architecture
|
|
lsrc_aarch64 += \
|
|
crc/aarch64/crc32_iscsi_refl_pmull.S \
|
|
crc/aarch64/crc32_gzip_refl_pmull.S \
|
|
crc/aarch64/crc32_iscsi_3crc_fold.S \
|
|
crc/aarch64/crc32_gzip_refl_3crc_fold.S \
|
|
crc/aarch64/crc32_iscsi_crc_ext.S \
|
|
crc/aarch64/crc32_gzip_refl_crc_ext.S \
|
|
crc/aarch64/crc32_mix_default.S \
|
|
crc/aarch64/crc32c_mix_default.S \
|
|
crc/aarch64/crc32_mix_neoverse_n1.S \
|
|
crc/aarch64/crc32c_mix_neoverse_n1.S
|
|
|