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https://github.com/intel/isa-l.git
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770 lines
21 KiB
NASM
770 lines
21 KiB
NASM
;;
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;; Copyright (c) 2023, Intel Corporation
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;;
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;; Redistribution and use in source and binary forms, with or without
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;; modification, are permitted provided that the following conditions are met:
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;;
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;; * Redistributions of source code must retain the above copyright notice,
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;; this list of conditions and the following disclaimer.
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;; * Redistributions in binary form must reproduce the above copyright
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;; notice, this list of conditions and the following disclaimer in the
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;; documentation and/or other materials provided with the distribution.
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;; * Neither the name of Intel Corporation nor the names of its contributors
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;; may be used to endorse or promote products derived from this software
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;; without specific prior written permission.
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;;
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;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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;; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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;; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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;; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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;; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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;; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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;; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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;; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;
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%ifndef __MEMCPY_INC__
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%define __MEMCPY_INC__
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%include "reg_sizes.asm"
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; This section defines a series of macros to copy small to medium amounts
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; of data from memory to memory, where the size is variable but limited.
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;
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; The macros are all called as:
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; memcpy DST, SRC, SIZE, TMP0, TMP1, XTMP0, XTMP1, XTMP2, XTMP3
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; with the parameters defined as:
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; DST : register: pointer to dst (not modified)
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; SRC : register: pointer to src (not modified)
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; SIZE : register: length in bytes (not modified)
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; TMP0 : 64-bit temp GPR (clobbered)
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; TMP1 : 64-bit temp GPR (clobbered)
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; XTMP0 : temp XMM (clobbered)
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; XTMP1 : temp XMM (clobbered)
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; XTMP2 : temp XMM (clobbered)
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; XTMP3 : temp XMM (clobbered)
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;
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; The name indicates the options. The name is of the form:
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; memcpy_<VEC>_<SZ><ZERO><RET>
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; where:
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; <VEC> is either "sse" or "avx" or "avx2"
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; <SZ> is either "64" or "128" and defines largest value of SIZE
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; <ZERO> is blank or "_1". If "_1" then the min SIZE is 1 (otherwise 0)
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; <RET> is blank or "_ret". If blank, the code falls through. If "ret"
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; it does a "ret" at the end
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;
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; For the avx2 versions, the temp XMM registers need to be YMM registers
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; If the SZ is 64, then only two YMM temps are needed, i.e. it is called as:
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; memcpy_avx2_64 DST, SRC, SIZE, TMP0, TMP1, YTMP0, YTMP1
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; memcpy_avx2_128 DST, SRC, SIZE, TMP0, TMP1, YTMP0, YTMP1, YTMP2, YTMP3
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;
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; For example:
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; memcpy_sse_64 : SSE, 0 <= size < 64, falls through
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; memcpy_avx_64_1 : AVX1, 1 <= size < 64, falls through
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; memcpy_sse_128_ret : SSE, 0 <= size < 128, ends with ret
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; mempcy_avx_128_1_ret : AVX1, 1 <= size < 128, ends with ret
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;
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%macro memcpy_sse_64 9
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__memcpy_int %1,%2,%3,%4,%5,%6,%7,%8,%9, 0, 64, 0, 0
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%endm
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%macro memcpy_sse_64_1 9
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__memcpy_int %1,%2,%3,%4,%5,%6,%7,%8,%9, 1, 64, 0, 0
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%endm
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%macro memcpy_sse_128 9
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__memcpy_int %1,%2,%3,%4,%5,%6,%7,%8,%9, 0, 128, 0, 0
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%endm
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%macro memcpy_sse_128_1 9
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__memcpy_int %1,%2,%3,%4,%5,%6,%7,%8,%9, 1, 128, 0, 0
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%endm
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%macro memcpy_sse_64_ret 9
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__memcpy_int %1,%2,%3,%4,%5,%6,%7,%8,%9, 0, 64, 1, 0
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%endm
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%macro memcpy_sse_64_1_ret 9
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__memcpy_int %1,%2,%3,%4,%5,%6,%7,%8,%9, 1, 64, 1, 0
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%endm
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%macro memcpy_sse_128_ret 9
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__memcpy_int %1,%2,%3,%4,%5,%6,%7,%8,%9, 0, 128, 1, 0
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%endm
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%macro memcpy_sse_128_1_ret 9
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__memcpy_int %1,%2,%3,%4,%5,%6,%7,%8,%9, 1, 128, 1, 0
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%endm
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%macro memcpy_sse_16 5
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__memcpy_int %1,%2,%3,%4,%5,,,,, 0, 16, 0, 0
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%endm
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%macro memcpy_sse_16_1 5
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__memcpy_int %1,%2,%3,%4,%5,,,,, 1, 16, 0, 0
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%endm
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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%macro memcpy_avx_64 9
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__memcpy_int %1,%2,%3,%4,%5,%6,%7,%8,%9, 0, 64, 0, 1
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%endm
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%macro memcpy_avx_64_1 9
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__memcpy_int %1,%2,%3,%4,%5,%6,%7,%8,%9, 1, 64, 0, 1
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%endm
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%macro memcpy_avx_128 9
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__memcpy_int %1,%2,%3,%4,%5,%6,%7,%8,%9, 0, 128, 0, 1
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%endm
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%macro memcpy_avx_128_1 9
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__memcpy_int %1,%2,%3,%4,%5,%6,%7,%8,%9, 1, 128, 0, 1
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%endm
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%macro memcpy_avx_64_ret 9
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__memcpy_int %1,%2,%3,%4,%5,%6,%7,%8,%9, 0, 64, 1, 1
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%endm
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%macro memcpy_avx_64_1_ret 9
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__memcpy_int %1,%2,%3,%4,%5,%6,%7,%8,%9, 1, 64, 1, 1
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%endm
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%macro memcpy_avx_128_ret 9
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__memcpy_int %1,%2,%3,%4,%5,%6,%7,%8,%9, 0, 128, 1, 1
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%endm
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%macro memcpy_avx_128_1_ret 9
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__memcpy_int %1,%2,%3,%4,%5,%6,%7,%8,%9, 1, 128, 1, 1
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%endm
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%macro memcpy_avx_16 5
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__memcpy_int %1,%2,%3,%4,%5,,,,, 0, 16, 0, 1
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%endm
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%macro memcpy_avx_16_1 5
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__memcpy_int %1,%2,%3,%4,%5,,,,, 1, 16, 0, 1
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%endm
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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%macro memcpy_avx2_64 7
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__memcpy_int %1,%2,%3,%4,%5,%6,%7,--,--, 0, 64, 0, 2
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%endm
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%macro memcpy_avx2_64_1 7
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__memcpy_int %1,%2,%3,%4,%5,%6,%7,--,--, 1, 64, 0, 2
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%endm
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%macro memcpy_avx2_128 9
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__memcpy_int %1,%2,%3,%4,%5,%6,%7, %8, %9, 0, 128, 0, 2
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%endm
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%macro memcpy_avx2_128_1 9
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__memcpy_int %1,%2,%3,%4,%5,%6,%7, %8, %9, 1, 128, 0, 2
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%endm
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%macro memcpy_avx2_64_ret 7
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__memcpy_int %1,%2,%3,%4,%5,%6,%7,--,--, 0, 64, 1, 2
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%endm
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%macro memcpy_avx2_64_1_ret 7
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__memcpy_int %1,%2,%3,%4,%5,%6,%7,--,--, 1, 64, 1, 2
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%endm
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%macro memcpy_avx2_128_ret 9
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__memcpy_int %1,%2,%3,%4,%5,%6,%7,%8,%9, 0, 128, 1, 2
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%endm
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%macro memcpy_avx2_128_1_ret 9
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__memcpy_int %1,%2,%3,%4,%5,%6,%7,%8,%9, 1, 128, 1, 2
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%endm
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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%macro __memcpy_int 13
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%define %%DST %1 ; register: pointer to dst (not modified)
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%define %%SRC %2 ; register: pointer to src (not modified)
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%define %%SIZE %3 ; register: length in bytes (not modified)
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%define %%TMP0 %4 ; 64-bit temp GPR (clobbered)
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%define %%TMP1 %5 ; 64-bit temp GPR (clobbered)
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%define %%XTMP0 %6 ; temp XMM (clobbered)
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%define %%XTMP1 %7 ; temp XMM (clobbered)
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%define %%XTMP2 %8 ; temp XMM (clobbered)
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%define %%XTMP3 %9 ; temp XMM (clobbered)
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%define %%NOT0 %10 ; if not 0, then assume size cannot be zero
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%define %%MAXSIZE %11 ; 128, 64, etc
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%define %%USERET %12 ; if not 0, use "ret" at end
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%define %%USEAVX %13 ; 0 = SSE, 1 = AVX1, 2 = AVX2
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%if (%%USERET != 0)
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%define %%DONE ret
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%else
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%define %%DONE jmp %%end
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%endif
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%if (%%USEAVX != 0)
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%define %%MOVDQU vmovdqu
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%else
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%define %%MOVDQU movdqu
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%endif
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%if (%%MAXSIZE >= 128)
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test %%SIZE, 64
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jz %%lt64
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%if (%%USEAVX >= 2)
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%%MOVDQU %%XTMP0, [%%SRC + 0*32]
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%%MOVDQU %%XTMP1, [%%SRC + 1*32]
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%%MOVDQU %%XTMP2, [%%SRC + %%SIZE - 2*32]
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%%MOVDQU %%XTMP3, [%%SRC + %%SIZE - 1*32]
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%%MOVDQU [%%DST + 0*32], %%XTMP0
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%%MOVDQU [%%DST + 1*32], %%XTMP1
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%%MOVDQU [%%DST + %%SIZE - 2*32], %%XTMP2
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%%MOVDQU [%%DST + %%SIZE - 1*32], %%XTMP3
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%else
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%%MOVDQU %%XTMP0, [%%SRC + 0*16]
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%%MOVDQU %%XTMP1, [%%SRC + 1*16]
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%%MOVDQU %%XTMP2, [%%SRC + 2*16]
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%%MOVDQU %%XTMP3, [%%SRC + 3*16]
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%%MOVDQU [%%DST + 0*16], %%XTMP0
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%%MOVDQU [%%DST + 1*16], %%XTMP1
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%%MOVDQU [%%DST + 2*16], %%XTMP2
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%%MOVDQU [%%DST + 3*16], %%XTMP3
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%%MOVDQU %%XTMP0, [%%SRC + %%SIZE - 4*16]
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%%MOVDQU %%XTMP1, [%%SRC + %%SIZE - 3*16]
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%%MOVDQU %%XTMP2, [%%SRC + %%SIZE - 2*16]
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%%MOVDQU %%XTMP3, [%%SRC + %%SIZE - 1*16]
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%%MOVDQU [%%DST + %%SIZE - 4*16], %%XTMP0
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%%MOVDQU [%%DST + %%SIZE - 3*16], %%XTMP1
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%%MOVDQU [%%DST + %%SIZE - 2*16], %%XTMP2
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%%MOVDQU [%%DST + %%SIZE - 1*16], %%XTMP3
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%endif
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%%DONE
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%endif
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%if (%%MAXSIZE >= 64)
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%%lt64:
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test %%SIZE, 32
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jz %%lt32
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%if (%%USEAVX >= 2)
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%%MOVDQU %%XTMP0, [%%SRC + 0*32]
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%%MOVDQU %%XTMP1, [%%SRC + %%SIZE - 1*32]
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%%MOVDQU [%%DST + 0*32], %%XTMP0
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%%MOVDQU [%%DST + %%SIZE - 1*32], %%XTMP1
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%else
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%%MOVDQU %%XTMP0, [%%SRC + 0*16]
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%%MOVDQU %%XTMP1, [%%SRC + 1*16]
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%%MOVDQU %%XTMP2, [%%SRC + %%SIZE - 2*16]
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%%MOVDQU %%XTMP3, [%%SRC + %%SIZE - 1*16]
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%%MOVDQU [%%DST + 0*16], %%XTMP0
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%%MOVDQU [%%DST + 1*16], %%XTMP1
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%%MOVDQU [%%DST + %%SIZE - 2*16], %%XTMP2
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%%MOVDQU [%%DST + %%SIZE - 1*16], %%XTMP3
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%endif
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%%DONE
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%endif
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%if (%%MAXSIZE >= 32)
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%%lt32:
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test %%SIZE, 16
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jz %%lt16
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%if (%%USEAVX >= 2)
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%%MOVDQU XWORD(%%XTMP0), [%%SRC + 0*16]
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%%MOVDQU XWORD(%%XTMP1), [%%SRC + %%SIZE - 1*16]
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%%MOVDQU [%%DST + 0*16], XWORD(%%XTMP0)
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%%MOVDQU [%%DST + %%SIZE - 1*16], XWORD(%%XTMP1)
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%else
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%%MOVDQU %%XTMP0, [%%SRC + 0*16]
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%%MOVDQU %%XTMP1, [%%SRC + %%SIZE - 1*16]
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%%MOVDQU [%%DST + 0*16], %%XTMP0
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%%MOVDQU [%%DST + %%SIZE - 1*16], %%XTMP1
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%endif
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%%DONE
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%endif
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%if (%%MAXSIZE >= 16)
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test %%SIZE, 16
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jz %%lt16
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mov %%TMP0, [%%SRC]
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mov %%TMP1, [%%SRC + 8]
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mov [%%DST], %%TMP0
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mov [%%DST + 8], %%TMP1
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%%lt16:
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test %%SIZE, 8
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jz %%lt8
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mov %%TMP0, [%%SRC]
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mov %%TMP1, [%%SRC + %%SIZE - 8]
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mov [%%DST], %%TMP0
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mov [%%DST + %%SIZE - 8], %%TMP1
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%%DONE
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%endif
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%if (%%MAXSIZE >= 8)
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%%lt8:
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test %%SIZE, 4
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jz %%lt4
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mov DWORD(%%TMP0), [%%SRC]
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mov DWORD(%%TMP1), [%%SRC + %%SIZE - 4]
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mov [%%DST], DWORD(%%TMP0)
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mov [%%DST + %%SIZE - 4], DWORD(%%TMP1)
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%%DONE
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%endif
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%if (%%MAXSIZE >= 4)
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%%lt4:
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test %%SIZE, 2
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jz %%lt2
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movzx DWORD(%%TMP0), word [%%SRC]
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movzx DWORD(%%TMP1), byte [%%SRC + %%SIZE - 1]
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mov [%%DST], WORD(%%TMP0)
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mov [%%DST + %%SIZE - 1], BYTE(%%TMP1)
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%%DONE
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%endif
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%%lt2:
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%if (%%NOT0 == 0)
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test %%SIZE, 1
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jz %%end
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%endif
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movzx DWORD(%%TMP0), byte [%%SRC]
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mov [%%DST], BYTE(%%TMP0)
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%%end:
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%if (%%USERET != 0)
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ret
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%endif
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%endm
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Utility macro to assist with SIMD shifting
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%macro _PSRLDQ 3
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%define %%VEC %1
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%define %%REG %2
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%define %%IMM %3
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%ifidn %%VEC, SSE
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psrldq %%REG, %%IMM
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%else
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vpsrldq %%REG, %%REG, %%IMM
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%endif
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%endm
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; This section defines a series of macros to store small to medium amounts
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; of data from SIMD registers to memory, where the size is variable but limited.
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;
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; The macros are all called as:
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; memcpy DST, SRC, SIZE, TMP, IDX
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; with the parameters defined as:
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; DST : register: pointer to dst (not modified)
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; SRC : register: src data (clobbered)
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; SIZE : register: length in bytes (not modified)
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; TMP : 64-bit temp GPR (clobbered)
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; IDX : 64-bit GPR to store dst index/offset (clobbered)
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; OFFSET ; Offset to be applied to destination pointer (optional)
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;
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; The name indicates the options. The name is of the form:
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; simd_store_<VEC>
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; where <VEC> is the SIMD instruction type e.g. "sse" or "avx"
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%macro simd_store_sse 5-6
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%if %0 == 6
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__simd_store %1,%2,%3,%4,%5,SSE,16,%6
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%else
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__simd_store %1,%2,%3,%4,%5,SSE,16
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%endif
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%endm
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%macro simd_store_avx 5-6
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%if %0 == 6
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__simd_store %1,%2,%3,%4,%5,AVX,16,%6
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%else
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__simd_store %1,%2,%3,%4,%5,AVX,16
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%endif
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%endm
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%macro simd_store_sse_15 5-6
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%if %0 == 6
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__simd_store %1,%2,%3,%4,%5,SSE,15,%6
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%else
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__simd_store %1,%2,%3,%4,%5,SSE,15
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%endif
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%endm
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%macro simd_store_avx_15 5-6
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%if %0 == 6
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__simd_store %1,%2,%3,%4,%5,AVX,15,%6
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%else
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__simd_store %1,%2,%3,%4,%5,AVX,15
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%endif
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%endm
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%macro __simd_store 7-8
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%define %%DST %1 ; register: pointer to dst (not modified)
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%define %%SRC %2 ; register: src data (clobbered)
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%define %%SIZE %3 ; register: length in bytes (not modified)
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%define %%TMP %4 ; 64-bit temp GPR (clobbered)
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%define %%IDX %5 ; 64-bit temp GPR to store dst idx (clobbered)
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%define %%SIMDTYPE %6 ; "SSE" or "AVX"
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%define %%MAX_LEN %7 ; maximum length to be stored
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%define %%OFFSET %8 ; offset to be applied to destination pointer
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%define %%PSRLDQ _PSRLDQ %%SIMDTYPE,
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%ifidn %%SIMDTYPE, SSE
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%define %%MOVDQU movdqu
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%define %%MOVQ movq
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%else
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%define %%MOVDQU vmovdqu
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%define %%MOVQ vmovq
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%endif
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;; determine max byte size for store operation
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%assign max_length_to_store %%MAX_LEN
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%if max_length_to_store > 16
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|
%error "__simd_store macro invoked with MAX_LEN bigger than 16!"
|
|
%endif
|
|
|
|
%if %0 == 8
|
|
mov %%IDX, %%OFFSET
|
|
%else
|
|
xor %%IDX, %%IDX ; zero idx
|
|
%endif
|
|
|
|
%if max_length_to_store == 16
|
|
test %%SIZE, 16
|
|
jz %%lt16
|
|
%%MOVDQU [%%DST + %%IDX], %%SRC
|
|
jmp %%end
|
|
%%lt16:
|
|
%endif
|
|
|
|
%if max_length_to_store >= 8
|
|
test %%SIZE, 8
|
|
jz %%lt8
|
|
%%MOVQ [%%DST + %%IDX], %%SRC
|
|
%%PSRLDQ %%SRC, 8
|
|
add %%IDX, 8
|
|
%%lt8:
|
|
%endif
|
|
|
|
%%MOVQ %%TMP, %%SRC ; use GPR from now on
|
|
|
|
%if max_length_to_store >= 4
|
|
test %%SIZE, 4
|
|
jz %%lt4
|
|
mov [%%DST + %%IDX], DWORD(%%TMP)
|
|
shr %%TMP, 32
|
|
add %%IDX, 4
|
|
%%lt4:
|
|
%endif
|
|
|
|
test %%SIZE, 2
|
|
jz %%lt2
|
|
mov [%%DST + %%IDX], WORD(%%TMP)
|
|
shr %%TMP, 16
|
|
add %%IDX, 2
|
|
%%lt2:
|
|
test %%SIZE, 1
|
|
jz %%end
|
|
mov [%%DST + %%IDX], BYTE(%%TMP)
|
|
%%end:
|
|
%endm
|
|
|
|
; This section defines a series of macros to load small to medium amounts
|
|
; (from 0 to 16 bytes) of data from memory to SIMD registers,
|
|
; where the size is variable but limited.
|
|
;
|
|
; The macros are all called as:
|
|
; simd_load DST, SRC, SIZE
|
|
; with the parameters defined as:
|
|
; DST : register: destination XMM register
|
|
; SRC : register: pointer to src data (not modified)
|
|
; SIZE : register: length in bytes (not modified)
|
|
;
|
|
; The name indicates the options. The name is of the form:
|
|
; simd_load_<VEC>_<SZ><ZERO>
|
|
; where:
|
|
; <VEC> is either "sse" or "avx"
|
|
; <SZ> is either "15" or "16" and defines largest value of SIZE
|
|
; <ZERO> is blank or "_1". If "_1" then the min SIZE is 1 (otherwise 0)
|
|
;
|
|
; For example:
|
|
; simd_load_sse_16 : SSE, 0 <= size <= 16
|
|
; simd_load_avx_15_1 : AVX, 1 <= size <= 15
|
|
|
|
%macro simd_load_sse_15_1 3
|
|
__simd_load %1,%2,%3,0,0,SSE
|
|
%endm
|
|
%macro simd_load_sse_15 3
|
|
__simd_load %1,%2,%3,1,0,SSE
|
|
%endm
|
|
%macro simd_load_sse_16_1 3
|
|
__simd_load %1,%2,%3,0,1,SSE
|
|
%endm
|
|
%macro simd_load_sse_16 3
|
|
__simd_load %1,%2,%3,1,1,SSE
|
|
%endm
|
|
|
|
%macro simd_load_avx_15_1 3
|
|
__simd_load %1,%2,%3,0,0,AVX
|
|
%endm
|
|
%macro simd_load_avx_15 3
|
|
__simd_load %1,%2,%3,1,0,AVX
|
|
%endm
|
|
%macro simd_load_avx_16_1 3
|
|
__simd_load %1,%2,%3,0,1,AVX
|
|
%endm
|
|
%macro simd_load_avx_16 3
|
|
__simd_load %1,%2,%3,1,1,AVX
|
|
%endm
|
|
|
|
%macro __simd_load 6
|
|
%define %%DST %1 ; [out] destination XMM register
|
|
%define %%SRC %2 ; [in] pointer to src data
|
|
%define %%SIZE %3 ; [in] length in bytes (0-16 bytes)
|
|
%define %%ACCEPT_0 %4 ; 0 = min length = 1, 1 = min length = 0
|
|
%define %%ACCEPT_16 %5 ; 0 = max length = 15 , 1 = max length = 16
|
|
%define %%SIMDTYPE %6 ; "SSE" or "AVX"
|
|
|
|
%ifidn %%SIMDTYPE, SSE
|
|
%define %%MOVDQU movdqu
|
|
%define %%PINSRB pinsrb
|
|
%define %%PINSRQ pinsrq
|
|
%define %%PXOR pxor
|
|
%else
|
|
%define %%MOVDQU vmovdqu
|
|
%define %%PINSRB vpinsrb
|
|
%define %%PINSRQ vpinsrq
|
|
%define %%PXOR vpxor
|
|
%endif
|
|
|
|
%if (%%ACCEPT_16 != 0)
|
|
test %%SIZE, 16
|
|
jz %%_skip_16
|
|
%%MOVDQU %%DST, [%%SRC]
|
|
jmp %%end_load
|
|
|
|
%%_skip_16:
|
|
%endif
|
|
%%PXOR %%DST, %%DST ; clear XMM register
|
|
%if (%%ACCEPT_0 != 0)
|
|
or %%SIZE, %%SIZE
|
|
je %%end_load
|
|
%endif
|
|
cmp %%SIZE, 2
|
|
jb %%_size_1
|
|
je %%_size_2
|
|
cmp %%SIZE, 4
|
|
jb %%_size_3
|
|
je %%_size_4
|
|
cmp %%SIZE, 6
|
|
jb %%_size_5
|
|
je %%_size_6
|
|
cmp %%SIZE, 8
|
|
jb %%_size_7
|
|
je %%_size_8
|
|
cmp %%SIZE, 10
|
|
jb %%_size_9
|
|
je %%_size_10
|
|
cmp %%SIZE, 12
|
|
jb %%_size_11
|
|
je %%_size_12
|
|
cmp %%SIZE, 14
|
|
jb %%_size_13
|
|
je %%_size_14
|
|
|
|
%%_size_15:
|
|
%%PINSRB %%DST, [%%SRC + 14], 14
|
|
%%_size_14:
|
|
%%PINSRB %%DST, [%%SRC + 13], 13
|
|
%%_size_13:
|
|
%%PINSRB %%DST, [%%SRC + 12], 12
|
|
%%_size_12:
|
|
%%PINSRB %%DST, [%%SRC + 11], 11
|
|
%%_size_11:
|
|
%%PINSRB %%DST, [%%SRC + 10], 10
|
|
%%_size_10:
|
|
%%PINSRB %%DST, [%%SRC + 9], 9
|
|
%%_size_9:
|
|
%%PINSRB %%DST, [%%SRC + 8], 8
|
|
%%_size_8:
|
|
%%PINSRQ %%DST, [%%SRC], 0
|
|
jmp %%end_load
|
|
%%_size_7:
|
|
%%PINSRB %%DST, [%%SRC + 6], 6
|
|
%%_size_6:
|
|
%%PINSRB %%DST, [%%SRC + 5], 5
|
|
%%_size_5:
|
|
%%PINSRB %%DST, [%%SRC + 4], 4
|
|
%%_size_4:
|
|
%%PINSRB %%DST, [%%SRC + 3], 3
|
|
%%_size_3:
|
|
%%PINSRB %%DST, [%%SRC + 2], 2
|
|
%%_size_2:
|
|
%%PINSRB %%DST, [%%SRC + 1], 1
|
|
%%_size_1:
|
|
%%PINSRB %%DST, [%%SRC + 0], 0
|
|
%%end_load:
|
|
%endm
|
|
|
|
%macro simd_load_avx2 5
|
|
%define %%DST %1 ; [out] destination YMM register
|
|
%define %%SRC %2 ; [in] pointer to src data
|
|
%define %%SIZE %3 ; [in] length in bytes (0-32 bytes)
|
|
%define %%IDX %4 ; [clobbered] Temp GP register to store src idx
|
|
%define %%TMP %5 ; [clobbered] Temp GP register
|
|
|
|
test %%SIZE, 32
|
|
jz %%_skip_32
|
|
vmovdqu %%DST, [%%SRC]
|
|
jmp %%end_load
|
|
|
|
%%_skip_32:
|
|
vpxor %%DST, %%DST ; clear YMM register
|
|
or %%SIZE, %%SIZE
|
|
je %%end_load
|
|
|
|
lea %%IDX, [%%SRC]
|
|
mov %%TMP, %%SIZE
|
|
cmp %%SIZE, 16
|
|
jle %%_check_size
|
|
|
|
add %%IDX, 16
|
|
sub %%TMP, 16
|
|
|
|
%%_check_size:
|
|
cmp %%TMP, 2
|
|
jb %%_size_1
|
|
je %%_size_2
|
|
cmp %%TMP, 4
|
|
jb %%_size_3
|
|
je %%_size_4
|
|
cmp %%TMP, 6
|
|
jb %%_size_5
|
|
je %%_size_6
|
|
cmp %%TMP, 8
|
|
jb %%_size_7
|
|
je %%_size_8
|
|
cmp %%TMP, 10
|
|
jb %%_size_9
|
|
je %%_size_10
|
|
cmp %%TMP, 12
|
|
jb %%_size_11
|
|
je %%_size_12
|
|
cmp %%TMP, 14
|
|
jb %%_size_13
|
|
je %%_size_14
|
|
cmp %%TMP, 15
|
|
je %%_size_15
|
|
|
|
%%_size_16:
|
|
vmovdqu XWORD(%%DST), [%%IDX]
|
|
jmp %%end_load
|
|
%%_size_15:
|
|
vpinsrb XWORD(%%DST), [%%IDX + 14], 14
|
|
%%_size_14:
|
|
vpinsrb XWORD(%%DST), [%%IDX + 13], 13
|
|
%%_size_13:
|
|
vpinsrb XWORD(%%DST), [%%IDX + 12], 12
|
|
%%_size_12:
|
|
vpinsrb XWORD(%%DST), [%%IDX + 11], 11
|
|
%%_size_11:
|
|
vpinsrb XWORD(%%DST), [%%IDX + 10], 10
|
|
%%_size_10:
|
|
vpinsrb XWORD(%%DST), [%%IDX + 9], 9
|
|
%%_size_9:
|
|
vpinsrb XWORD(%%DST), [%%IDX + 8], 8
|
|
%%_size_8:
|
|
vpinsrq XWORD(%%DST), [%%IDX], 0
|
|
jmp %%_check_higher_16
|
|
%%_size_7:
|
|
vpinsrb XWORD(%%DST), [%%IDX + 6], 6
|
|
%%_size_6:
|
|
vpinsrb XWORD(%%DST), [%%IDX + 5], 5
|
|
%%_size_5:
|
|
vpinsrb XWORD(%%DST), [%%IDX + 4], 4
|
|
%%_size_4:
|
|
vpinsrb XWORD(%%DST), [%%IDX + 3], 3
|
|
%%_size_3:
|
|
vpinsrb XWORD(%%DST), [%%IDX + 2], 2
|
|
%%_size_2:
|
|
vpinsrb XWORD(%%DST), [%%IDX + 1], 1
|
|
%%_size_1:
|
|
vpinsrb XWORD(%%DST), [%%IDX + 0], 0
|
|
%%_check_higher_16:
|
|
test %%SIZE, 16
|
|
jz %%end_load
|
|
|
|
; Move last bytes loaded to upper half and load 16 bytes in lower half
|
|
vinserti128 %%DST, XWORD(%%DST), 1
|
|
vinserti128 %%DST, [%%SRC], 0
|
|
%%end_load:
|
|
%endm
|
|
|
|
%macro simd_store_avx2 5
|
|
%define %%DST %1 ; register: pointer to dst (not modified)
|
|
%define %%SRC %2 ; register: src data (clobbered)
|
|
%define %%SIZE %3 ; register: length in bytes (not modified)
|
|
%define %%TMP %4 ; 64-bit temp GPR (clobbered)
|
|
%define %%IDX %5 ; 64-bit temp GPR to store dst idx (clobbered)
|
|
|
|
xor %%IDX, %%IDX ; zero idx
|
|
|
|
test %%SIZE, 32
|
|
jz %%lt32
|
|
vmovdqu [%%DST], %%SRC
|
|
jmp %%end
|
|
%%lt32:
|
|
|
|
test %%SIZE, 16
|
|
jz %%lt16
|
|
vmovdqu [%%DST], XWORD(%%SRC)
|
|
; Move upper half to lower half for further stores
|
|
vperm2i128 %%SRC, %%SRC, %%SRC, 0x81
|
|
add %%IDX, 16
|
|
%%lt16:
|
|
|
|
test %%SIZE, 8
|
|
jz %%lt8
|
|
vmovq [%%DST + %%IDX], XWORD(%%SRC)
|
|
vpsrldq XWORD(%%SRC), 8
|
|
add %%IDX, 8
|
|
%%lt8:
|
|
|
|
vmovq %%TMP, XWORD(%%SRC) ; use GPR from now on
|
|
|
|
test %%SIZE, 4
|
|
jz %%lt4
|
|
mov [%%DST + %%IDX], DWORD(%%TMP)
|
|
shr %%TMP, 32
|
|
add %%IDX, 4
|
|
%%lt4:
|
|
|
|
test %%SIZE, 2
|
|
jz %%lt2
|
|
mov [%%DST + %%IDX], WORD(%%TMP)
|
|
shr %%TMP, 16
|
|
add %%IDX, 2
|
|
%%lt2:
|
|
test %%SIZE, 1
|
|
jz %%end
|
|
mov [%%DST + %%IDX], BYTE(%%TMP)
|
|
%%end:
|
|
%endm
|
|
|
|
%endif ; ifndef __MEMCPY_INC__
|