Daniel Gregory 726a6f7c02 build: Add riscv64 support ...

Use the base implementations for every function.

Signed-off-by: Daniel Gregory <daniel.gregory@bytedance.com>

2025-03-20 19:22:40 +00:00

..

aarch64

raid: reformat using new code style

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Makefile.am

build: Add riscv64 support

2025-03-20 19:22:40 +00:00

pq_check_sse_i32.asm

Remove all slver legacy segments

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pq_check_sse.asm

raid: remove unneeded load

2023-12-11 09:31:11 +00:00

pq_check_test.c

raid: reformat using new code style

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pq_gen_avx2.asm

Remove all slver legacy segments

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pq_gen_avx512.asm

x86: Add ENDBR32/ENDBR64 at function entries for Intel CET

2020-05-26 09:16:49 -07:00

pq_gen_avx.asm

Remove all slver legacy segments

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pq_gen_perf.c

raid: reformat using new code style

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pq_gen_sse_i32.asm

Remove all slver legacy segments

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pq_gen_sse.asm

Remove all slver legacy segments

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pq_gen_test.c

raid: reformat using new code style

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raid_base_aliases.c

raid: reformat using new code style

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raid_base.c

raid: reformat using new code style

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raid_multibinary_i32.asm

multibinary: move WRT_OPT macro to common header

2017-08-18 14:24:57 -07:00

raid_multibinary.asm

Remove all slver legacy segments

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xor_check_sse.asm

Fix a handful of spelling mistakes and typos

2024-02-06 15:03:14 +00:00

xor_check_test.c

raid: reformat using new code style

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xor_example.c

raid: reformat using new code style

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xor_gen_avx512.asm

x86: Add ENDBR32/ENDBR64 at function entries for Intel CET

2020-05-26 09:16:49 -07:00

xor_gen_avx.asm

Remove all slver legacy segments

2022-07-14 19:23:52 -07:00

xor_gen_perf.c

raid: reformat using new code style

2024-04-22 11:35:03 +02:00

xor_gen_sse.asm

Remove all slver legacy segments

2022-07-14 19:23:52 -07:00

xor_gen_test.c

raid: reformat using new code style

2024-04-22 11:35:03 +02:00