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https://github.com/intel/isa-l.git
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2bbce31943
- Added reference implementation - Added base implementation - Added functional and performance tests Change-Id: I60c5097bd5fb89ee7a50910e71d449d50d155d0a Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com> Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
60 lines
2.6 KiB
Makefile
60 lines
2.6 KiB
Makefile
########################################################################
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# Copyright(c) 2020 Arm Corporation All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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# * Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# * Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in
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# the documentation and/or other materials provided with the
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# distribution.
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# * Neither the name of Arm Corporation nor the names of its
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# contributors may be used to endorse or promote products derived
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# from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#########################################################################
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lsrc_aarch64 += \
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crc/aarch64/crc_multibinary_arm.S \
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crc/aarch64/crc_aarch64_dispatcher.c
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lsrc_aarch64 += \
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crc/aarch64/crc16_t10dif_pmull.S \
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crc/aarch64/crc16_t10dif_copy_pmull.S \
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crc/aarch64/crc32_ieee_norm_pmull.S \
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crc/aarch64/crc64_ecma_refl_pmull.S \
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crc/aarch64/crc64_ecma_norm_pmull.S \
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crc/aarch64/crc64_iso_refl_pmull.S \
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crc/aarch64/crc64_iso_norm_pmull.S \
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crc/aarch64/crc64_jones_refl_pmull.S \
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crc/aarch64/crc64_jones_norm_pmull.S \
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crc/aarch64/crc64_rocksoft.c
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#CRC32/CRC32C for micro-architecture
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lsrc_aarch64 += \
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crc/aarch64/crc32_iscsi_refl_pmull.S \
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crc/aarch64/crc32_gzip_refl_pmull.S \
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crc/aarch64/crc32_iscsi_3crc_fold.S \
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crc/aarch64/crc32_gzip_refl_3crc_fold.S \
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crc/aarch64/crc32_iscsi_crc_ext.S \
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crc/aarch64/crc32_gzip_refl_crc_ext.S \
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crc/aarch64/crc32_mix_default.S \
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crc/aarch64/crc32c_mix_default.S \
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crc/aarch64/crc32_mix_neoverse_n1.S \
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crc/aarch64/crc32c_mix_neoverse_n1.S
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