mirror of
https://github.com/intel/isa-l.git
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9f75defd57
The relic slver is no longer used for individual versioning on functions and is confusing tools looking for data in text sections. This removes all instances instead of fixing since its usefulness is waining. Fixes #221 Change-Id: Ife0b9f105950a90337c58e8a41ac2cffc0f67d99 Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
393 lines
9.7 KiB
NASM
393 lines
9.7 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; * Neither the name of Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;
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;;; gf_3vect_dot_prod_avx2(len, vec, *g_tbls, **buffs, **dests);
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;;;
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%include "reg_sizes.asm"
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%ifidn __OUTPUT_FORMAT__, elf64
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%define arg0 rdi
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%define arg1 rsi
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%define arg2 rdx
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%define arg3 rcx
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%define arg4 r8
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%define arg5 r9
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%define tmp r11
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%define tmp.w r11d
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%define tmp.b r11b
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%define tmp2 r10
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%define tmp3 r13 ; must be saved and restored
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%define tmp4 r12 ; must be saved and restored
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%define return rax
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%macro SLDR 2
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%endmacro
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%define SSTR SLDR
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%define PS 8
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%define LOG_PS 3
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%define func(x) x: endbranch
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%macro FUNC_SAVE 0
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push r12
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push r13
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%endmacro
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%macro FUNC_RESTORE 0
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pop r13
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pop r12
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%endmacro
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%endif
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%ifidn __OUTPUT_FORMAT__, win64
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%define arg0 rcx
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%define arg1 rdx
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%define arg2 r8
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%define arg3 r9
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%define arg4 r12 ; must be saved, loaded and restored
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%define arg5 r15 ; must be saved and restored
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%define tmp r11
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%define tmp.w r11d
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%define tmp.b r11b
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%define tmp2 r10
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%define tmp3 r13 ; must be saved and restored
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%define tmp4 r14 ; must be saved and restored
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%define return rax
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%macro SLDR 2
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%endmacro
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%define SSTR SLDR
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%define PS 8
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%define LOG_PS 3
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%define stack_size 6*16 + 5*8 ; must be an odd multiple of 8
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%define arg(x) [rsp + stack_size + PS + PS*x]
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%define func(x) proc_frame x
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%macro FUNC_SAVE 0
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alloc_stack stack_size
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vmovdqa [rsp + 0*16], xmm6
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vmovdqa [rsp + 1*16], xmm7
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vmovdqa [rsp + 2*16], xmm8
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vmovdqa [rsp + 3*16], xmm9
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vmovdqa [rsp + 4*16], xmm10
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vmovdqa [rsp + 5*16], xmm11
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save_reg r12, 6*16 + 0*8
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save_reg r13, 6*16 + 1*8
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save_reg r14, 6*16 + 2*8
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save_reg r15, 6*16 + 3*8
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end_prolog
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mov arg4, arg(4)
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%endmacro
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%macro FUNC_RESTORE 0
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vmovdqa xmm6, [rsp + 0*16]
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vmovdqa xmm7, [rsp + 1*16]
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vmovdqa xmm8, [rsp + 2*16]
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vmovdqa xmm9, [rsp + 3*16]
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vmovdqa xmm10, [rsp + 4*16]
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vmovdqa xmm11, [rsp + 5*16]
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mov r12, [rsp + 6*16 + 0*8]
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mov r13, [rsp + 6*16 + 1*8]
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mov r14, [rsp + 6*16 + 2*8]
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mov r15, [rsp + 6*16 + 3*8]
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add rsp, stack_size
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%endmacro
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%endif
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%ifidn __OUTPUT_FORMAT__, elf32
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;;;================== High Address;
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;;; arg4
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;;; arg3
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;;; arg2
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;;; arg1
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;;; arg0
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;;; return
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;;;<================= esp of caller
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;;; ebp
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;;;<================= ebp = esp
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;;; var0
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;;; var1
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;;; esi
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;;; edi
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;;; ebx
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;;;<================= esp of callee
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;;;
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;;;================== Low Address;
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%define PS 4
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%define LOG_PS 2
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%define func(x) x: endbranch
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%define arg(x) [ebp + PS*2 + PS*x]
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%define var(x) [ebp - PS - PS*x]
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%define trans ecx
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%define trans2 esi
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%define arg0 trans ;trans and trans2 are for the variables in stack
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%define arg0_m arg(0)
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%define arg1 ebx
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%define arg2 arg2_m
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%define arg2_m arg(2)
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%define arg3 trans
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%define arg3_m arg(3)
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%define arg4 trans
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%define arg4_m arg(4)
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%define arg5 trans2
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%define tmp edx
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%define tmp.w edx
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%define tmp.b dl
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%define tmp2 edi
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%define tmp3 trans2
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%define tmp3_m var(0)
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%define tmp4 trans2
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%define tmp4_m var(1)
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%define return eax
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%macro SLDR 2 ;stack load/restore
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mov %1, %2
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%endmacro
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%define SSTR SLDR
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%macro FUNC_SAVE 0
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push ebp
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mov ebp, esp
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sub esp, PS*2 ;2 local variables
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push esi
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push edi
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push ebx
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mov arg1, arg(1)
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%endmacro
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%macro FUNC_RESTORE 0
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pop ebx
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pop edi
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pop esi
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add esp, PS*2 ;2 local variables
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pop ebp
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%endmacro
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%endif ; output formats
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%define len arg0
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%define vec arg1
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%define mul_array arg2
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%define src arg3
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%define dest1 arg4
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%define ptr arg5
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%define vec_i tmp2
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%define dest2 tmp3
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%define dest3 tmp4
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%define pos return
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%ifidn PS,4 ;32-bit code
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%define len_m arg0_m
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%define src_m arg3_m
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%define dest1_m arg4_m
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%define dest2_m tmp3_m
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%define dest3_m tmp4_m
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%endif
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%ifndef EC_ALIGNED_ADDR
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;;; Use Un-aligned load/store
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%define XLDR vmovdqu
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%define XSTR vmovdqu
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%else
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;;; Use Non-temporal load/stor
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%ifdef NO_NT_LDST
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%define XLDR vmovdqa
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%define XSTR vmovdqa
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%else
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%define XLDR vmovntdqa
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%define XSTR vmovntdq
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%endif
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%endif
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%ifidn PS,8 ;64-bit code
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default rel
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[bits 64]
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%endif
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section .text
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%ifidn PS,8 ;64-bit code
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%define xmask0f ymm11
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%define xmask0fx xmm11
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%define xgft1_lo ymm10
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%define xgft1_hi ymm9
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%define xgft2_lo ymm8
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%define xgft2_hi ymm7
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%define xgft3_lo ymm6
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%define xgft3_hi ymm5
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%define x0 ymm0
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%define xtmpa ymm1
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%define xp1 ymm2
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%define xp2 ymm3
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%define xp3 ymm4
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%else
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%define xmask0f ymm7
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%define xmask0fx xmm7
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%define xgft1_lo ymm6
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%define xgft1_hi ymm5
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%define xgft2_lo xgft1_lo
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%define xgft2_hi xgft1_hi
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%define xgft3_lo xgft1_lo
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%define xgft3_hi xgft1_hi
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%define x0 ymm0
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%define xtmpa ymm1
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%define xp1 ymm2
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%define xp2 ymm3
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%define xp3 ymm4
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%endif
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align 16
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mk_global gf_3vect_dot_prod_avx2, function
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func(gf_3vect_dot_prod_avx2)
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FUNC_SAVE
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SLDR len, len_m
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sub len, 32
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SSTR len_m, len
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jl .return_fail
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xor pos, pos
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mov tmp.b, 0x0f
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vpinsrb xmask0fx, xmask0fx, tmp.w, 0
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vpbroadcastb xmask0f, xmask0fx ;Construct mask 0x0f0f0f...
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sal vec, LOG_PS ;vec *= PS. Make vec_i count by PS
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SLDR dest1, dest1_m
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mov dest2, [dest1+PS]
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SSTR dest2_m, dest2
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mov dest3, [dest1+2*PS]
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SSTR dest3_m, dest3
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mov dest1, [dest1]
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SSTR dest1_m, dest1
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.loop32:
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vpxor xp1, xp1
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vpxor xp2, xp2
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vpxor xp3, xp3
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mov tmp, mul_array
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xor vec_i, vec_i
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.next_vect:
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SLDR src, src_m
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mov ptr, [src+vec_i]
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vmovdqu xgft1_lo, [tmp] ;Load array Ax{00}, Ax{01}, ..., Ax{0f}
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; " Ax{00}, Ax{10}, ..., Ax{f0}
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vperm2i128 xgft1_hi, xgft1_lo, xgft1_lo, 0x11 ; swapped to hi | hi
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vperm2i128 xgft1_lo, xgft1_lo, xgft1_lo, 0x00 ; swapped to lo | lo
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%ifidn PS,8 ; 64-bit code
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vmovdqu xgft2_lo, [tmp+vec*(32/PS)] ;Load array Bx{00}, Bx{01}, ..., Bx{0f}
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; " Bx{00}, Bx{10}, ..., Bx{f0}
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vperm2i128 xgft2_hi, xgft2_lo, xgft2_lo, 0x11 ; swapped to hi | hi
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vperm2i128 xgft2_lo, xgft2_lo, xgft2_lo, 0x00 ; swapped to lo | lo
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vmovdqu xgft3_lo, [tmp+vec*(64/PS)] ;Load array Cx{00}, Cx{01}, ..., Cx{0f}
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; " Cx{00}, Cx{10}, ..., Cx{f0}
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vperm2i128 xgft3_hi, xgft3_lo, xgft3_lo, 0x11 ; swapped to hi | hi
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vperm2i128 xgft3_lo, xgft3_lo, xgft3_lo, 0x00 ; swapped to lo | lo
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add tmp, 32
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add vec_i, PS
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%endif
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XLDR x0, [ptr+pos] ;Get next source vector
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vpand xtmpa, x0, xmask0f ;Mask low src nibble in bits 4-0
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vpsraw x0, x0, 4 ;Shift to put high nibble into bits 4-0
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vpand x0, x0, xmask0f ;Mask high src nibble in bits 4-0
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vpshufb xgft1_hi, x0 ;Lookup mul table of high nibble
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vpshufb xgft1_lo, xtmpa ;Lookup mul table of low nibble
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vpxor xgft1_hi, xgft1_lo ;GF add high and low partials
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vpxor xp1, xgft1_hi ;xp1 += partial
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%ifidn PS,4 ; 32-bit code
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vmovdqu xgft2_lo, [tmp+vec*(32/PS)] ;Load array Bx{00}, Bx{01}, ..., Bx{0f}
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; " Bx{00}, Bx{10}, ..., Bx{f0}
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vperm2i128 xgft2_hi, xgft2_lo, xgft2_lo, 0x11 ; swapped to hi | hi
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vperm2i128 xgft2_lo, xgft2_lo, xgft2_lo, 0x00 ; swapped to lo | lo
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%endif
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vpshufb xgft2_hi, x0 ;Lookup mul table of high nibble
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vpshufb xgft2_lo, xtmpa ;Lookup mul table of low nibble
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vpxor xgft2_hi, xgft2_lo ;GF add high and low partials
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vpxor xp2, xgft2_hi ;xp2 += partial
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%ifidn PS,4 ; 32-bit code
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sal vec, 1
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vmovdqu xgft3_lo, [tmp+vec*(32/PS)] ;Load array Cx{00}, Cx{01}, ..., Cx{0f}
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; " Cx{00}, Cx{10}, ..., Cx{f0}
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vperm2i128 xgft3_hi, xgft3_lo, xgft3_lo, 0x11 ; swapped to hi | hi
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vperm2i128 xgft3_lo, xgft3_lo, xgft3_lo, 0x00 ; swapped to lo | lo
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sar vec, 1
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add tmp, 32
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add vec_i, PS
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%endif
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vpshufb xgft3_hi, x0 ;Lookup mul table of high nibble
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vpshufb xgft3_lo, xtmpa ;Lookup mul table of low nibble
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vpxor xgft3_hi, xgft3_lo ;GF add high and low partials
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vpxor xp3, xgft3_hi ;xp3 += partial
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cmp vec_i, vec
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jl .next_vect
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SLDR dest1, dest1_m
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SLDR dest2, dest2_m
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XSTR [dest1+pos], xp1
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XSTR [dest2+pos], xp2
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SLDR dest3, dest3_m
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XSTR [dest3+pos], xp3
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SLDR len, len_m
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add pos, 32 ;Loop on 32 bytes at a time
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cmp pos, len
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jle .loop32
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lea tmp, [len + 32]
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cmp pos, tmp
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je .return_pass
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;; Tail len
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mov pos, len ;Overlapped offset length-16
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jmp .loop32 ;Do one more overlap pass
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.return_pass:
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mov return, 0
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FUNC_RESTORE
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ret
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.return_fail:
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mov return, 1
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FUNC_RESTORE
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ret
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endproc_frame
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