mirror of
https://github.com/intel/isa-l.git
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0de3661ec0
banana_f3:
new: xor_gen_warm: runtime = 3006459 usecs, bandwidth 10685 MB in 3.0065 sec = 3554.17 MB/s
old: xor_gen_warm: runtime = 3060970 usecs, bandwidth 514 MB in 3.0610 sec = 168.21 MB/s
Signed-off-by: sunyuechi <sunyuechi@iscas.ac.cn>
83 lines
3.2 KiB
ArmAsm
83 lines
3.2 KiB
ArmAsm
/**********************************************************************
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Copyright (c) 2025 Institute of Software Chinese Academy of Sciences (ISCAS).
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of ISCAS nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**********************************************************************/
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#if HAVE_RVV
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.option arch, +v
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.global xor_gen_rvv
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.type xor_gen_rvv, %function
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xor_gen_rvv:
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beqz a1, ret0 # len <= 0, return 0
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addi t1, a0, -2 # vects - 3
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blez t1, ret1 # vects < 3, return 1
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slli t0, a0, 3 # t0 = vects * 8
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add t0, a2, t0 # array + vects * 8
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ld a4, 0(a2) # src[0]
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ld a3, -8(t0) # dest = array[vects - 1]
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mv t5, a3 # save dest
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mv t6, a1 # save len
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init_dest:
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vsetvli t4, t6, e8, m8, ta, ma
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vle8.v v0, (a4) # load src[0]
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vse8.v v0, (a3) # dest
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sub t6, t6, t4
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add a4, a4, t4
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add a3, a3, t4
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bnez t6, init_dest
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outer_j:
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mv a3, t5 # restore dest
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mv t6, a1 # restore length
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ld a4, -16(t0)
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inner_len:
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vsetvli t4, t6, e8, m8, ta, ma
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vle8.v v0, (a4) # src[j]
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vle8.v v8, (a3) # dest
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vxor.vv v8, v8, v0 # dest ^= src[j]
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vse8.v v8, (a3)
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sub t6, t6, t4
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add a4, a4, t4
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add a3, a3, t4
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bnez t6, inner_len
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addi t1, t1, -1
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addi t0, t0, -8
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bnez t1, outer_j
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ret0:
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li a0, 0
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ret
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ret1:
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li a0, 1
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ret
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#endif
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