mirror of
https://github.com/intel/isa-l.git
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ba874ba762
banana_f3:
new: pq_gen_warm: runtime = 3062397 usecs, bandwidth 4737 MB in 3.0624 sec = 1546.92 MB/s
old: pq_gen_warm: runtime = 3005894 usecs, bandwidth 2851 MB in 3.0059 sec = 948.80 MB/s
Signed-off-by: sunyuechi <sunyuechi@iscas.ac.cn>
106 lines
4.5 KiB
ArmAsm
106 lines
4.5 KiB
ArmAsm
/**********************************************************************
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Copyright (c) 2025 Institute of Software Chinese Academy of Sciences (ISCAS).
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of ISCAS nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**********************************************************************/
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#if HAVE_RVV
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.option arch, +v
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.global pq_gen_rvv
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.type pq_gen_rvv, %function
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pq_gen_rvv:
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srli a1, a1, 3 // blocks = len / 8
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beqz a1, ret0 // blocks <= 0
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addi a6, a0, -3 // j = vects - 4
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blez a6, ret1 // vects < 4
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slli t0, a0, 3 // t0 = vects * 8
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add t0, a2, t0 // array + vects * 8
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li t1, 0x8080808080808080 // bit7
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li t2, 0xfefefefefefefefe // notbit0
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li t3, 0x1d1d1d1d1d1d1d1d // gf8poly
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ld a3, -24(t0) // src[vects-3]
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ld a4, -16(t0) // p
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ld a5, -8(t0) // q
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mv t6, a1 // save blocks
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mv t5, a4 // save p
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mv a7, a5 // save q
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init_pq:
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vsetvli t4, t6, e64, m4, ta, ma
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vle64.v v0, (a3)
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vse64.v v0, (a4) // init p
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vse64.v v0, (a5) // init q
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sub t6, t6, t4
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slli t4, t4, 3
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add a3, a3, t4
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add a4, a4, t4
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add a5, a5, t4
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bnez t6, init_pq
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outer_j:
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mv a4, t5 // restore p
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mv a5, a7 // restore q
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mv t6, a1 // restore blocks
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ld a0, -32(t0) // src[j]
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inner_block:
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vsetvli t4, t6, e64, m4, ta, ma
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vle64.v v8, (a0) // s
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vle64.v v0, (a4) // p
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vle64.v v4, (a5) // q
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vxor.vv v0, v0, v8 // p ^= s
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vand.vx v20, v4, t1 // q & bit7
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vsll.vi v24, v4, 1 // (q << 1)
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vand.vx v24, v24, t2 // (q << 1) & notbit0
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vsrl.vi v16, v20, 7 // (q & bit7)>>7
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vsll.vi v20, v20, 1 // (q & bit7)<<1
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vsub.vv v20, v20, v16 // (q & bit7)<<1 - (q & bit7)>>7
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vand.vx v20, v20, t3 // ((q & bit7)<<1 - (q & bit7)>>7) & gf8poly
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vxor.vv v4, v24, v20 // ((q << 1) & notbit0) ^
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vxor.vv v4, v4, v8 // s^
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vse64.v v0, (a4) // p
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vse64.v v4, (a5) // q
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sub t6, t6, t4 // blocks
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slli t4, t4, 3
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add a4, a4, t4 // p+=
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add a5, a5, t4 // q+=
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add a0, a0, t4 // s+=
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bnez t6, inner_block
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addi a6, a6, -1
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addi t0, t0, -8
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bnez a6, outer_j
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ret0:
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li a0, 0
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ret
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ret1:
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li a0, 1
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ret
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#endif
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