mirror of
https://github.com/intel/isa-l.git
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1187583a97
- It should be fine to enable pmull always on Apple Silicon - macOS 12+ is required for PMULL instruction. - Changed the conditional macro to __APPLE__ - Rewritten dispatcher using sysctlbyname - Use __USER_LABEL_PREFIX__ - Use __TEXT,__const as readonly section - use ASM_DEF_RODATA macro - fix func decl Change-Id: I800593f21085d8187b480c8bb3ab2bd70c4a6974 Signed-off-by: Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>
209 lines
5.9 KiB
ArmAsm
209 lines
5.9 KiB
ArmAsm
/**********************************************************************
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Copyright(c) 2019 Arm Corporation All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of Arm Corporation nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**********************************************************************/
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#include "../include/aarch64_label.h"
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.arch armv8-a
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.text
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.align 2
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#include "lz0a_const_aarch64.h"
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#include "data_struct_aarch64.h"
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#include "huffman_aarch64.h"
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#include "bitbuf2_aarch64.h"
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#include "stdmac_aarch64.h"
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/*
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declare Macros
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*/
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.macro declare_generic_reg name:req,reg:req,default:req
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\name .req \default\reg
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w_\name .req w\reg
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x_\name .req x\reg
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.endm
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.text
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.align 2
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.global cdecl(set_long_icf_fg_aarch64)
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#ifndef __APPLE__
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.type set_long_icf_fg_aarch64, %function
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#endif
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/*
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void set_long_icf_fg_aarch64(uint8_t * next_in, uint64_t processed, uint64_t input_size,
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struct deflate_icf *match_lookup)
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*/
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/* arguments */
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declare_generic_reg next_in_param, 0,x
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declare_generic_reg processed_param, 1,x
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declare_generic_reg input_size_param, 2,x
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declare_generic_reg match_lookup_param, 3,x
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declare_generic_reg param0, 0,x
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declare_generic_reg param1, 1,x
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declare_generic_reg param2, 2,x
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/* local variable */
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declare_generic_reg len, 7,w
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declare_generic_reg dist_code, 8,w
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declare_generic_reg shortest_match_len, 9,w
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declare_generic_reg len_max, 10,w
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declare_generic_reg dist_extra, 11,w
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declare_generic_reg const_8, 13,x
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declare_generic_reg next_in, 20,x
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declare_generic_reg dist_start, 21,x
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declare_generic_reg end_processed, 22,x
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declare_generic_reg end_in, 23,x
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declare_generic_reg match_lookup, 19,x
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declare_generic_reg match_length, 4,w
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declare_generic_reg tmp0, 5,w
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declare_generic_reg tmp1, 6,w
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/* constant */
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.equ DIST_START_SIZE, 128
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.equ ISAL_LOOK_AHEAD, 288
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.equ LEN_OFFSET, 254
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.equ SHORTEST_MATCH, 4
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.equ LEN_MAX_CONST, 512
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cdecl(set_long_icf_fg_aarch64):
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stp x29, x30, [sp, -192]!
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add x29, sp, 0
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stp x21, x22, [sp, 32]
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add x21, x29, 64
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stp x19, x20, [sp, 16]
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str x23, [sp, 48]
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add end_processed, next_in_param, processed_param
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mov next_in, next_in_param
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add end_in, next_in_param, input_size_param
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mov match_lookup, match_lookup_param
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#ifndef __APPLE__
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adrp x1, .data_dist_start
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mov x2, DIST_START_SIZE // 128
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add x1, x1, :lo12:.data_dist_start
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mov x0, dist_start
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#else
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adrp x1, .data_dist_start@PAGE
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mov x2, DIST_START_SIZE // 128
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add x1, x1, .data_dist_start@PAGEOFF
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mov x0, dist_start
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#endif
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bl cdecl(memcpy)
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add x_tmp0, end_processed, ISAL_LOOK_AHEAD // 288
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cmp end_in, x_tmp0
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csel end_in, end_in, x_tmp0, cc
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cmp next_in, end_processed
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bcs .done
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mov const_8, 8
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mov len_max, LEN_MAX_CONST // 512
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mov shortest_match_len, (LEN_OFFSET + SHORTEST_MATCH - 1)
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b .while_outer_loop
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.align 2
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.while_outer_check:
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add next_in, next_in, 1
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add match_lookup, match_lookup, 4
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cmp end_processed, next_in
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bls .done
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.while_outer_loop:
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ldrh len, [match_lookup]
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and len, len, LIT_LEN_MASK // 1023
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cmp len, (LEN_OFFSET + 8 - 1) // 261
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bls .while_outer_check
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ldr dist_code, [match_lookup]
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add x1, next_in, 8
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ldrh dist_extra, [match_lookup, 2]
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sub w2, w_end_in, w1
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ubfx x_dist_code, x_dist_code, 10, 9
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ubfx x_dist_extra, x_dist_extra, 3, 13
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uxtw x0, dist_code
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ldr w0, [dist_start, x0, lsl 2]
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add w0, dist_extra, w0
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sub x0, const_8, x0
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add x0, next_in, x0
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compare_aarch64 param0,param1,param2,match_length,tmp0,tmp1
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mov w0, w_match_length
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add w0, w0, (LEN_OFFSET + 8) // 262
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cmp w0, len
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bls .while_outer_check
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lsl w2, dist_extra, 19
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orr w2, w2, dist_code, lsl 10
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.align 3
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.while_inner_loop:
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cmp w0, LEN_MAX_CONST // 512
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add next_in, next_in, 1
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csel w1, w0, len_max, ls
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sub w0, w0, #1
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orr w1, w1, w2
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str w1, [match_lookup]
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ldrh w1, [match_lookup, 4]!
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and w1, w1, LIT_LEN_MASK // 1023
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cmp w1, (LEN_OFFSET + SHORTEST_MATCH - 1) // 257
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csel w1, w1, shortest_match_len, cs
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cmp w1, w0
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bcc .while_inner_loop
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add next_in, next_in, 1
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add match_lookup, match_lookup, 4
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cmp end_processed, next_in
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bhi .while_outer_loop
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.done:
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ldp x19, x20, [sp, 16]
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ldp x21, x22, [sp, 32]
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ldr x23, [sp, 48]
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ldp x29, x30, [sp], 192
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ret
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#ifndef __APPLE__
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.size set_long_icf_fg_aarch64, .-set_long_icf_fg_aarch64
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#endif
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ASM_DEF_RODATA
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.align 3
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.set .data_dist_start,. + 0
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.real_data_dist_start:
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.word 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0007, 0x0009, 0x000d
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.word 0x0011, 0x0019, 0x0021, 0x0031, 0x0041, 0x0061, 0x0081, 0x00c1
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.word 0x0101, 0x0181, 0x0201, 0x0301, 0x0401, 0x0601, 0x0801, 0x0c01
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.word 0x1001, 0x1801, 0x2001, 0x3001, 0x4001, 0x6001, 0x0000, 0x0000
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