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d414b2702a
The ISA-L EC code has been written using RVV vector instructions and the minimum multiplication table, resulting in a performance improvement of over 10 times compared to the existing implementation. Signed-off-by: Shuo Lv <lv.shuo@sanechips.com.cn>
115 lines
3.4 KiB
ArmAsm
115 lines
3.4 KiB
ArmAsm
##################################################################
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# Copyright (c) 2025 sanechips Technologies Co., Ltd.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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# * Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# * Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in
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# the documentation and/or other materials provided with the
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# distribution.
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# * Neither the name of sanechips Corporation nor the names of its
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# contributors may be used to endorse or promote products derived
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# from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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########################################################################
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#if HAVE_RVV
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.text
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.align 2
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.global gf_vect_mul_rvv
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.type gf_vect_mul_rvv, @function
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/* Function arguments:
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* a0: len - Length of vector in bytes.
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* a1: gftbl - Pointer to 32-byte array of pre-calculated constants.
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* a2: src - Pointer to source data array.
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* a3: dest - Pointer to destination data array.
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* Returns:
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* a0: 0 for success, 1 for failure.
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*/
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/* Local variables */
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#define x_pos t0
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#define x_tmp t1
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#define x_ptr t2
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#define x_len a0
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#define x_tbl a1
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#define x_src a2
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#define x_dest a3
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/* Vector registers */
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#define v_src v1
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#define v_src_lo v2
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#define v_src_hi v3
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#define v_dest v4
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#define v_tmp1_lo v5
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#define v_tmp1_hi v6
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#define v_gft1_lo v7
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#define v_gft1_hi v8
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gf_vect_mul_rvv:
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/* Check if len is 32 bytes */
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andi x_tmp, x_len, 0x1F
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bnez x_tmp, .return_fail
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vsetvli t6, x0, e8, m1
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/* Load pre-calculated constants into v_gft1_lo and v_gft1_hi */
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vle8.v v_gft1_lo, (x_tbl)
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addi t3, x_tbl, 16
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vle8.v v_gft1_hi, (t3)
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/* Initialize position counter */
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li x_pos, 0
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.Llooprvv_vl:
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/* Load source data into v_src */
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add x_ptr,x_src,x_pos
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vle8.v v_src, (x_ptr)
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/* Split 4-bit lo and 4-bit hi */
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vand.vi v_src_lo, v_src, 0x0F
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vsrl.vi v_src_hi, v_src, 4
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/* Table lookup (GF multiplication) */
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vrgather.vv v_tmp1_lo, v_gft1_lo, v_src_lo
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vrgather.vv v_tmp1_hi, v_gft1_hi, v_src_hi
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/* XOR (GF addition) */
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vxor.vv v_dest, v_tmp1_hi, v_tmp1_lo
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/* Store result to destination */
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vse8.v v_dest, (x_dest)
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/* Increment position counter */
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add x_pos, x_pos, t6
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add x_dest, x_dest, t6
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/* Check if we have processed all bytes */
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blt x_pos, x_len, .Llooprvv_vl
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.return_pass:
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li a0, 0
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ret
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.return_fail:
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li a0, 1
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ret
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#endif
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