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d414b2702a
The ISA-L EC code has been written using RVV vector instructions and the minimum multiplication table, resulting in a performance improvement of over 10 times compared to the existing implementation. Signed-off-by: Shuo Lv <lv.shuo@sanechips.com.cn>
137 lines
4.5 KiB
ArmAsm
137 lines
4.5 KiB
ArmAsm
##################################################################
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# Copyright (c) 2025 sanechips Technologies Co., Ltd.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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# * Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# * Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in
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# the documentation and/or other materials provided with the
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# distribution.
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# * Neither the name of sanechips Corporation nor the names of its
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# contributors may be used to endorse or promote products derived
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# from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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########################################################################
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# RISC-V RVV implementation of gf_vect_dot_prod_rvv
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# Function: gf_vect_dot_prod_rvv
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# Arguments:
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# a0: len (vector length)
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# a1: vlen (number of source vectors)
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# a2: gftbls (pointer to GF(2^8) multiplication tables)
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# a3: src (pointer to array of source vector pointers)
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# a4: dest (pointer to destination vector)
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# Local variables:
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# t0: vec_i (source vector index)
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# t1: ptr (pointer to current source vector)
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# t2: pos (current position in vector)
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# t3: tbl1 (pointer to current GF table)
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# Vector registers:
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# v0: z_mask0f (mask for low 4 bits)
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# v1: z_src (source vector data)
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# v2: z_src_lo (low 4 bits of source vector)
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# v3: z_src_hi (high 4 bits of source vector)
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# v4: z_dest (destination vector)
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# v5: z_gft1_lo (low 8 bits of GF table)
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# v6: z_gft1_hi (high 8 bits of GF table)
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#if HAVE_RVV
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.global gf_vect_dot_prod_rvv
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.type gf_vect_dot_prod_rvv, @function
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gf_vect_dot_prod_rvv:
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# Check if len < 16
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li t4, 16
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blt a0, t4, .return_fail
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vsetvli t5, zero, e8, m1 # Set vector length to maximum
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# Initialize pos = 0
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li t2, 0
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# Multiply vlen by 8 (each pointer is 8 bytes)
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slli a1, a1, 3
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.Llooprvv_vl:
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# Check if pos >= len
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bge t2, a0, .return_pass
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# Clear z_dest
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vmv.v.i v4, 0
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# Initialize vec_i = 0
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li t0, 0
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# Reset tbl1 to gftbls
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mv t3, a2
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.Llooprvv_vl_vects:
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# Load src[vec_i] into ptr
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add t6, a3, t0 # src + vec_i * 8
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ld t1, 0(t6) # Load pointer to current source vector
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# Load src data into z_src
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add t1, t1, t2 # add offset
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vle8.v v1, (t1) # Load source vector into v1
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# Increment vec_i
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addi t0, t0, 8
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# Load GF table (low and high)
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vle8.v v5, (t3) # Load low 8 bits of GF table
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addi t3, t3, 16 # Move to next GF table entry
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vle8.v v6, (t3) # Load high 8 bits of GF table
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addi t3, t3, 16 # Move to next GF table entry
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# Split src into low and high 4 bits
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vand.vi v2, v1, 0x0F # z_src_lo = z_src & z_mask0f
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vsrl.vi v3, v1, 4 # z_src_hi = z_src >> 4
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# GF multiplication (table lookup)
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vrgather.vv v8, v5, v2 # z_gft1_lo = GF table lookup for low 4 bits
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vrgather.vv v9, v6, v3 # z_gft1_hi = GF table lookup for high 4 bits
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# GF addition (XOR)
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vxor.vv v4, v4, v8 # z_dest ^= z_gft1_lo
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vxor.vv v4, v4, v9 # z_dest ^= z_gft1_hi
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# Check if vec_i < vlen
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blt t0, a1, .Llooprvv_vl_vects
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# Store z_dest to dest[pos]
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vse8.v v4, (a4) # Store destination vector
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add a4, a4, t5 # Move dest pointer to next position
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# Increment pos
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add t2, t2, t5 # pos += 16 (vector length)
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j .Llooprvv_vl
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.return_pass:
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li a0, 0 # Return 0 (success)
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ret
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.return_fail:
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li a0, 1 # Return 1 (failure)
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ret
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#endif
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