mirror of
https://github.com/intel/isa-l.git
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d414b2702a
The ISA-L EC code has been written using RVV vector instructions and the minimum multiplication table, resulting in a performance improvement of over 10 times compared to the existing implementation. Signed-off-by: Shuo Lv <lv.shuo@sanechips.com.cn>
215 lines
5.5 KiB
ArmAsm
215 lines
5.5 KiB
ArmAsm
##################################################################
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# Copyright (c) 2025 sanechips Technologies Co., Ltd.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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# * Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# * Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in
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# the documentation and/or other materials provided with the
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# distribution.
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# * Neither the name of sanechips Corporation nor the names of its
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# contributors may be used to endorse or promote products derived
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# from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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########################################################################
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#if HAVE_RVV
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.text
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.align 2
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.global gf_5vect_mad_rvv
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.type gf_5vect_mad_rvv, @function
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/* gf_5vect_mad_rvv(int len, int vec, int vec_i, unsigned char *gftbls,
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unsigned char *src, unsigned char **dest);
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*/
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/* arguments */
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#define x_len a0
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#define x_vec a1
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#define x_vec_i a2
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#define x_tbl a3
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#define x_src a4
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#define x_dest a5
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/* returns */
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#define w_ret a0
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/* local variables */
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#define x_pos t0
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#define x_dest1 t1
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#define x_dest2 t2
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#define x_dest3 t3
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#define x_dest4 t4
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#define x_dest5 t5
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/* vectors */
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#define v_src v1
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#define v_src_lo v2
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#define v_src_hi v3
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#define v_dest1 v4
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#define v_tmp_lo v5
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#define v_tmp_hi v6
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#define v_gft1_lo v7
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#define v_gft1_hi v8
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#define v_gft2_lo v9
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#define v_gft2_hi v10
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#define v_gft3_lo v11
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#define v_gft3_hi v12
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#define v_gft4_lo v13
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#define v_gft4_hi v14
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#define v_gft5_lo v15
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#define v_gft5_hi v16
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#define v_dest2 v19
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#define v_dest3 v20
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#define v_dest4 v21
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#define v_dest5 v22
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gf_5vect_mad_rvv:
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/* less than 16 bytes, return_fail */
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li t6, 16
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blt x_len, t6, .return_fail
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vsetvli a7, x0, e8, m1
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/* Load table 1 */
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slli a6, x_vec_i, 5
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add x_tbl, x_tbl, a6
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vle8.v v_gft1_lo, (x_tbl)
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addi a6, x_tbl, 16
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vle8.v v_gft1_hi, (a6)
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/* Load table 2 */
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slli a6, x_vec, 5
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add x_tbl, x_tbl, a6
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vle8.v v_gft2_lo, (x_tbl)
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addi a6, x_tbl, 16
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vle8.v v_gft2_hi, (a6)
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/* Load table 3 */
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slli a6, x_vec, 5
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add x_tbl, x_tbl, a6
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vle8.v v_gft3_lo, (x_tbl)
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addi a6, x_tbl, 16
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vle8.v v_gft3_hi, (a6)
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/* Load table 4 */
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slli a6, x_vec, 5
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add x_tbl, x_tbl, a6
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vle8.v v_gft4_lo, (x_tbl)
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addi a6, x_tbl, 16
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vle8.v v_gft4_hi, (a6)
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/* Load table 5 */
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slli a6, x_vec, 5
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add x_tbl, x_tbl, a6
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vle8.v v_gft5_lo, (x_tbl)
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addi a6, x_tbl, 16
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vle8.v v_gft5_hi, (a6)
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/* Load destination pointers */
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ld x_dest1, 0(x_dest)
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ld x_dest2, 8(x_dest)
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ld x_dest3, 16(x_dest)
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ld x_dest4, 24(x_dest)
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ld x_dest5, 32(x_dest)
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li x_pos, 0
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.Llooprvv_vl:
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blt x_pos, x_len, .Lloop_body
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j .return_pass
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.Lloop_body:
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/* Load source data */
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add t6, x_src, x_pos
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vle8.v v_src, (t6)
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/* Split 4-bit lo; 4-bit hi */
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vand.vi v_src_lo, v_src, 0x0F
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vsrl.vi v_src_hi, v_src, 4
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/* load dest data */
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add t6, x_dest1, x_pos
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vle8.v v_dest1, (t6)
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add t6, x_dest2, x_pos
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vle8.v v_dest2, (t6)
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add t6, x_dest3, x_pos
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vle8.v v_dest3, (t6)
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add t6, x_dest4, x_pos
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vle8.v v_dest4, (t6)
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add t6, x_dest5, x_pos
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vle8.v v_dest5, (t6)
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/* dest1 */
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vrgather.vv v_tmp_lo, v_gft1_lo, v_src_lo
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vrgather.vv v_tmp_hi, v_gft1_hi, v_src_hi
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vxor.vv v_dest1, v_tmp_lo, v_dest1
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vxor.vv v_dest1, v_tmp_hi, v_dest1
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/* dest2 */
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vrgather.vv v_tmp_lo, v_gft2_lo, v_src_lo
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vrgather.vv v_tmp_hi, v_gft2_hi, v_src_hi
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vxor.vv v_dest2, v_tmp_lo, v_dest2
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vxor.vv v_dest2, v_tmp_hi, v_dest2
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/* dest3 */
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vrgather.vv v_tmp_lo, v_gft3_lo, v_src_lo
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vrgather.vv v_tmp_hi, v_gft3_hi, v_src_hi
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vxor.vv v_dest3, v_tmp_lo, v_dest3
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vxor.vv v_dest3, v_tmp_hi, v_dest3
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/* dest4 */
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vrgather.vv v_tmp_lo, v_gft4_lo, v_src_lo
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vrgather.vv v_tmp_hi, v_gft4_hi, v_src_hi
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vxor.vv v_dest4, v_tmp_lo, v_dest4
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vxor.vv v_dest4, v_tmp_hi, v_dest4
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/* dest5 */
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vrgather.vv v_tmp_lo, v_gft5_lo, v_src_lo
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vrgather.vv v_tmp_hi, v_gft5_hi, v_src_hi
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vxor.vv v_dest5, v_tmp_lo, v_dest5
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vxor.vv v_dest5, v_tmp_hi, v_dest5
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/* Store destination data */
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add t6, x_dest1, x_pos
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vse8.v v_dest1, (t6)
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add t6, x_dest2, x_pos
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vse8.v v_dest2, (t6)
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add t6, x_dest3, x_pos
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vse8.v v_dest3, (t6)
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add t6, x_dest4, x_pos
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vse8.v v_dest4, (t6)
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add t6, x_dest5, x_pos
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vse8.v v_dest5, (t6)
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/* Increment position */
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add x_pos, x_pos, a7
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j .Llooprvv_vl
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.return_pass:
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li w_ret, 0
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ret
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.return_fail:
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li w_ret, 1
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ret
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#endif
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