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https://github.com/intel/isa-l.git
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d414b2702a
The ISA-L EC code has been written using RVV vector instructions and the minimum multiplication table, resulting in a performance improvement of over 10 times compared to the existing implementation. Signed-off-by: Shuo Lv <lv.shuo@sanechips.com.cn>
243 lines
6.2 KiB
ArmAsm
243 lines
6.2 KiB
ArmAsm
##################################################################
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# Copyright (c) 2025 sanechips Technologies Co., Ltd.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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# * Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# * Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in
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# the documentation and/or other materials provided with the
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# distribution.
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# * Neither the name of sanechips Corporation nor the names of its
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# contributors may be used to endorse or promote products derived
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# from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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########################################################################
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#if HAVE_RVV
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.text
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.align 2
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.global gf_5vect_dot_prod_rvv
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.type gf_5vect_dot_prod_rvv, @function
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/* void gf_5vect_dot_prod_rvv(int len, int vlen, unsigned char *gftbls,
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unsigned char **src, unsigned char **dest);
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*/
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/* arguments */
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#define x_len a0 /* vector length */
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#define x_vec a1 /* number of source vectors (ie. data blocks) */
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#define x_tbl a2
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#define x_src a3
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#define x_dest a4
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/* local variables */
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#define x_vec_i a7
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#define x_ptr t1
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#define x_pos t2
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#define x_tbl1 t3
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#define x_tbl2 t4
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#define x_tbl3 t5
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#define x_tbl4 t6
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#define x_tbl5 s0
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#define x_dest1 s1
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#define x_dest2 s2
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#define x_dest3 s3
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#define x_dest4 s4
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#define x_dest5 s5
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/* vectors */
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#define v_src v1
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#define v_src_lo v2
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#define v_src_hi v3
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#define v_dest1 v4
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#define v_gft1_lo v5
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#define v_gft1_hi v6
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#define v_gft2_lo v7
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#define v_gft2_hi v8
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#define v_gft3_lo v9
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#define v_gft3_hi v10
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#define v_gft4_lo v11
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#define v_gft4_hi v12
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#define v_gft5_lo v13
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#define v_gft5_hi v14
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#define v_dest2 v15
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#define v_dest3 v16
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#define v_dest4 v17
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#define v_dest5 v18
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gf_5vect_dot_prod_rvv:
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/* less than 16 bytes, return_fail */
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li t0, 16
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blt x_len, t0, .return_fail
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/* save s0-s4 */
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addi sp, sp, -48
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sd s0, 0(sp)
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sd s1, 8(sp)
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sd s2, 16(sp)
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sd s3, 24(sp)
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sd s4, 32(sp)
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sd s5, 40(sp)
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vsetvli a5, x0, e8, m1
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/* Initialize position */
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li x_pos, 0
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/* Load destination pointers */
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ld x_dest1, 0(x_dest)
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ld x_dest2, 8(x_dest)
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ld x_dest3, 16(x_dest)
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ld x_dest4, 24(x_dest)
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ld x_dest5, 32(x_dest)
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/* Loop 1: x_len, vector length */
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.Llooprvv_vl:
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bge x_pos, x_len, .return_pass
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/* Clear destination vectors */
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vmv.v.i v_dest1, 0
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vmv.v.i v_dest2, 0
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vmv.v.i v_dest3, 0
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vmv.v.i v_dest4, 0
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vmv.v.i v_dest5, 0
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/* Reset table pointers */
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mv x_tbl1, x_tbl
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slli t0, x_vec, 5
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add x_tbl2, x_tbl1, t0
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add x_tbl3, x_tbl2, t0
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add x_tbl4, x_tbl3, t0
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add x_tbl5, x_tbl4, t0
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/* Loop 2: x_vec, number of source vectors (ie. data blocks) */
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li x_vec_i, 0
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.Llooprvv_vl_vects:
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/* Load source data */
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slli a6, x_vec_i, 3
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add a6,x_src,a6
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ld x_ptr, 0(a6)
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add x_ptr, x_ptr, x_pos
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vle8.v v_src, (x_ptr)
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/* Split 4-bit lo; 4-bit hi */
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vand.vi v_src_lo, v_src, 0x0F
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vsrl.vi v_src_hi, v_src, 4
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/* Load gf_table's */
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vle8.v v_gft1_lo, (x_tbl1)
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addi x_tbl1, x_tbl1, 16
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vle8.v v_gft1_hi, (x_tbl1)
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addi x_tbl1, x_tbl1, 16
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vle8.v v_gft2_lo, (x_tbl2)
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addi x_tbl2, x_tbl2, 16
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vle8.v v_gft2_hi, (x_tbl2)
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addi x_tbl2, x_tbl2, 16
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/* Move to next source vector */
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addi x_vec_i, x_vec_i, 1
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/* dest 1 */
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vrgather.vv v26, v_gft1_lo, v_src_lo
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vrgather.vv v27, v_gft1_hi, v_src_hi
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vxor.vv v_dest1, v_dest1, v26
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vxor.vv v_dest1, v_dest1, v27
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/* Load more gf_table's */
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vle8.v v_gft3_lo, (x_tbl3)
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addi x_tbl3, x_tbl3, 16
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vle8.v v_gft3_hi, (x_tbl3)
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addi x_tbl3, x_tbl3, 16
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vle8.v v_gft4_lo, (x_tbl4)
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addi x_tbl4, x_tbl4, 16
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vle8.v v_gft4_hi, (x_tbl4)
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addi x_tbl4, x_tbl4, 16
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/* dest 2 */
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vrgather.vv v26, v_gft2_lo, v_src_lo
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vrgather.vv v27, v_gft2_hi, v_src_hi
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vxor.vv v_dest2, v_dest2, v26
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vxor.vv v_dest2, v_dest2, v27
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/* dest 3 */
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vrgather.vv v26, v_gft3_lo, v_src_lo
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vrgather.vv v27, v_gft3_hi, v_src_hi
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vxor.vv v_dest3, v_dest3, v26
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vxor.vv v_dest3, v_dest3, v27
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/* Load more gf_table's */
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vle8.v v_gft5_lo, (x_tbl5)
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addi x_tbl5, x_tbl5, 16
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vle8.v v_gft5_hi, (x_tbl5)
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addi x_tbl5, x_tbl5, 16
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/* dest 4 */
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vrgather.vv v26, v_gft4_lo, v_src_lo
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vrgather.vv v27, v_gft4_hi, v_src_hi
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vxor.vv v_dest4, v_dest4, v26
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vxor.vv v_dest4, v_dest4, v27
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/* dest 5 */
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vrgather.vv v26, v_gft5_lo, v_src_lo
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vrgather.vv v27, v_gft5_hi, v_src_hi
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vxor.vv v_dest5, v_dest5, v26
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vxor.vv v_dest5, v_dest5, v27
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/* Check if we have processed all vectors */
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blt x_vec_i, x_vec, .Llooprvv_vl_vects
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vse8.v v_dest1, (x_dest1)
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vse8.v v_dest2, (x_dest2)
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vse8.v v_dest3, (x_dest3)
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vse8.v v_dest4, (x_dest4)
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vse8.v v_dest5, (x_dest5)
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/* Store destination data */
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add x_dest1,x_dest1,a5
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add x_dest2,x_dest2,a5
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add x_dest3,x_dest3,a5
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add x_dest4,x_dest4,a5
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add x_dest5,x_dest5,a5
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/* Increment position */
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add x_pos, x_pos, a5
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j .Llooprvv_vl
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.return_pass:
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/* Restore callee-saved registers */
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ld s0, 0(sp)
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ld s1, 8(sp)
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ld s2, 16(sp)
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ld s3, 24(sp)
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ld s4, 32(sp)
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ld s5, 40(sp)
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addi sp, sp, 48
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li a0, 0
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ret
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.return_fail:
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li a0, 1
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ret
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#endif
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