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4 Commits

Author SHA1 Message Date
Hong Bo Peng
180c74aefd enable VSX SIMD in ISA-L for ppc64le 
1) Implement the ErasureCode function in Altivec Intrinsics
  2) Coding style update

Change-Id: I2c81d035f4083e9b011dbf3b741f628813b68606
Thanks-to: Daniel Axtens <dja@axtens.net>
Signed-off-by: Hong Bo Peng <penghb@cn.ibm.com>
 2020-02-20 09:40:43 -07:00
zhiyuan.zhu
2d6c8496f2 mem: mem-zero-detect optimization on Arm64 
Change-Id: I9e7b8c80657c9c251d69efcfc73acc53567cfa33
Signed-off-by: Zhiyuan Zhu <zhiyuan.zhu@arm.com>
 2019-02-22 08:15:22 +00:00
Yibo Cai
7a44098a98 build: Add aarch64 support 
Change-Id: If9594936a28355d89edd1a331b3b429dffa44184
Signed-off-by: Yibo Cai <yibo.cai@arm.com>
 2019-02-10 13:08:56 -07:00
John Kariuki
6e2013391a mem: Add zero detect memory functions 
This patch introduces the base, avx and sse optimized zero detect memory function.
The zero detect memory function tests if a memory region is all zeroes. If all the
bytes in the memory region are zero, the function return a zero. Otherwise, if the
memory region has non zero bytes, the zero detect function returns a 1.

Change-Id: If965badf750377124d0067d09f888d0419554998
Signed-off-by: John Kariuki <John.K.Kariuki@intel.com>
 2018-09-25 14:33:31 -07:00