Commit Graph

10 Commits

Author SHA1 Message Date
Jerry Yu
183385f02f multibinary: Add run-time cpu feature detect for aarch64
Some CPUs  report "illegal instruction" error for the crc test because
they do not support the relevant optional feature . This can be fixed by
introducing CPU feature detection for AArch64 .

The difference with the x86 implementation is the dispatcher . It is based
on the glibc function `getauxval(AT_HWCAP)` and `getauxval(AT_HWCAP2)` , not
registers or instructions .

On a  heterogeneous system (big.LITTLE) , it is dangerous to detect CPU
features using identification registers . And while it is possible to use
architectural feature registers from userspace on recent kernels, this
won't necessarily work with older platforms . Thus we use the HW_CAPs
exported from the kernel (and visible in getauxval) as the solution.

- According to kernel suggestion , getauxval should be used for this purpose .
  - [CPU Feature detection](https://github.com/torvalds/linux/blob/master/Documentation/arm64/cpu-feature-registers.rst)
- According to  AAPCS result/paramter registers should be saved/restore for function call
  - [AAPCS](http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs64.pdf)
  - [GLibc](https://sourceware.org/git/gitweb.cgi?p=glibc.git;a=blob;f=sysdeps/aarch64/dl-trampoline.S)

Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>
Change-Id: Ic9abe0d2268ac95537e1abf10acc642fc58a5054
2019-08-26 17:58:42 +08:00
Roy Oursler
699bb5bd3f all: Revamp performance testing to be time based
Change-Id: I6260d28e4adc974d8db0a1c770e3eb922d87f8e4
Signed-off-by: Roy Oursler <roy.j.oursler@intel.com>
2019-03-07 09:28:04 -07:00
Roy Oursler
a3169750b5 mem: Remove unaligned loads in base function
Change-Id: I8fb0f2e2e372485c864d5c60f816b661a865b707
Signed-off-by: Roy Oursler <roy.j.oursler@intel.com>
2019-03-07 09:27:50 -07:00
Roy Oursler
733901ee32 mem: Change test r and l data type to avoid unsigned add overflow
Change-Id: If9c30c5fda72ed5139a7cab01b5236f57a3ad0ef
Signed-off-by: Roy Oursler <roy.j.oursler@intel.com>
2019-03-07 09:27:50 -07:00
Zhiyuan Zhu
636272cff6 aarch64: Fix dynamic lib call crash
If an application treats these functions as function pointers, and this
lib (isa-l) is compiled into solib, a segmentation fault may occur.

For example: Ubuntu 16.04 on arm64 platfrom will be crash, because the
linker does not know that this symbol is a function, so mark the function
type explicitly with %function to solves this issue.

Change-Id: Iba41b1f1367146d7dcce09203694b08b1cb8ec20
Signed-off-by: Zhiyuan Zhu <zhiyuan.zhu@arm.com>
2019-03-01 02:55:50 +00:00
zhiyuan.zhu
2d6c8496f2 mem: mem-zero-detect optimization on Arm64
Change-Id: I9e7b8c80657c9c251d69efcfc73acc53567cfa33
Signed-off-by: Zhiyuan Zhu <zhiyuan.zhu@arm.com>
2019-02-22 08:15:22 +00:00
Yibo Cai
7a44098a98 build: Add aarch64 support
Change-Id: If9594936a28355d89edd1a331b3b429dffa44184
Signed-off-by: Yibo Cai <yibo.cai@arm.com>
2019-02-10 13:08:56 -07:00
Greg Tucker
2e212f28fa build: Fix for mac nasm lack of symbol types
Change-Id: I9ee86a3e32876d3860477c8365fc459d94a8920e
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2018-11-29 13:54:36 -07:00
Greg Tucker
8ddc8d0117 mem: Fix zero detect base function for mingw
Mingw does not define WORDSIZE and incorrect int width was used.

Change-Id: Idc9f560dd1c722d51f6e54ba2342feafa13f8fa5
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2018-09-26 10:32:31 -07:00
John Kariuki
6e2013391a mem: Add zero detect memory functions
This patch introduces the base, avx and sse optimized zero detect memory function.
The zero detect memory function tests if a memory region is all zeroes. If all the
bytes in the memory region are zero, the function return a zero. Otherwise, if the
memory region has non zero bytes, the zero detect function returns a 1.

Change-Id: If965badf750377124d0067d09f888d0419554998
Signed-off-by: John Kariuki <John.K.Kariuki@intel.com>
2018-09-25 14:33:31 -07:00