Commit Graph

16 Commits

Author SHA1 Message Date
Roy Oursler
d3caab9c3a build: Avoid requiring AVX512 define when using dispatch functions
Change-Id: I76af2d6ab7eb61ae531bbc7427650d08737c20ab
Signed-off-by: Roy Oursler <roy.j.oursler@intel.com>
2019-09-14 16:01:28 -07:00
Jerry Yu
183385f02f multibinary: Add run-time cpu feature detect for aarch64
Some CPUs  report "illegal instruction" error for the crc test because
they do not support the relevant optional feature . This can be fixed by
introducing CPU feature detection for AArch64 .

The difference with the x86 implementation is the dispatcher . It is based
on the glibc function `getauxval(AT_HWCAP)` and `getauxval(AT_HWCAP2)` , not
registers or instructions .

On a  heterogeneous system (big.LITTLE) , it is dangerous to detect CPU
features using identification registers . And while it is possible to use
architectural feature registers from userspace on recent kernels, this
won't necessarily work with older platforms . Thus we use the HW_CAPs
exported from the kernel (and visible in getauxval) as the solution.

- According to kernel suggestion , getauxval should be used for this purpose .
  - [CPU Feature detection](https://github.com/torvalds/linux/blob/master/Documentation/arm64/cpu-feature-registers.rst)
- According to  AAPCS result/paramter registers should be saved/restore for function call
  - [AAPCS](http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs64.pdf)
  - [GLibc](https://sourceware.org/git/gitweb.cgi?p=glibc.git;a=blob;f=sysdeps/aarch64/dl-trampoline.S)

Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>
Change-Id: Ic9abe0d2268ac95537e1abf10acc642fc58a5054
2019-08-26 17:58:42 +08:00
Roy Oursler
699bb5bd3f all: Revamp performance testing to be time based
Change-Id: I6260d28e4adc974d8db0a1c770e3eb922d87f8e4
Signed-off-by: Roy Oursler <roy.j.oursler@intel.com>
2019-03-07 09:28:04 -07:00
Zhiyuan Zhu
636272cff6 aarch64: Fix dynamic lib call crash
If an application treats these functions as function pointers, and this
lib (isa-l) is compiled into solib, a segmentation fault may occur.

For example: Ubuntu 16.04 on arm64 platfrom will be crash, because the
linker does not know that this symbol is a function, so mark the function
type explicitly with %function to solves this issue.

Change-Id: Iba41b1f1367146d7dcce09203694b08b1cb8ec20
Signed-off-by: Zhiyuan Zhu <zhiyuan.zhu@arm.com>
2019-03-01 02:55:50 +00:00
Zhiyuan Zhu
f5aa9d72de raid: Add license headers
Change-Id: I0d2d48eb30c31ff6967c132a415431dddd8a8982
Signed-off-by: Zhiyuan Zhu <zhiyuan.zhu@arm.com>
2019-02-22 14:32:19 -07:00
Yibo Cai
19fb012e81 raid: Add aarch64 NEON implementation
Change-Id: I6ad471d3b22a87bfa7e216713e04afa990a90edb
Signed-off-by: Yibo Cai <yibo.cai@arm.com>
2019-02-10 13:08:56 -07:00
Yibo Cai
7a44098a98 build: Add aarch64 support
Change-Id: If9594936a28355d89edd1a331b3b429dffa44184
Signed-off-by: Yibo Cai <yibo.cai@arm.com>
2019-02-10 13:08:56 -07:00
Greg Tucker
2e212f28fa build: Fix for mac nasm lack of symbol types
Change-Id: I9ee86a3e32876d3860477c8365fc459d94a8920e
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2018-11-29 13:54:36 -07:00
Greg Tucker
9e79faeeff raid: Ensure example meets min align requirement
Change-Id: Ie9d367176046bb4919474981c84e957bed6c99d6
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2018-03-06 13:39:32 -07:00
Greg Tucker
5af4e4aa0a raid: Change example to use multi-binary function
Change-Id: I9a3edf4ad0b9b8afad6d0545bfc7436b4c8fdfe0
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2018-03-01 13:32:54 -07:00
Xiaodong Liu
3ab8239097 multibinary: move WRT_OPT macro to common header
Signed-off-by: Xiaodong Liu <xiaodong.liu@intel.com>
2017-08-18 14:24:57 -07:00
Greg Tucker
fc1467deb2 Format only patch from iindent and remove_whitespace
Change-Id: I114bfcfa8750c7ba3a50ad2be9dd9e87cb7a1042
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2017-06-26 04:10:47 -04:00
Greg Tucker
8f1155387c raid: Add avx512 version of pq_gen
Change-Id: Ic404e7f3c09c953fe3687355cc3f9728cfd16011
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2017-03-30 20:22:36 -07:00
Greg Tucker
0a62b7c40d raid: Add avx512 version of xor
Change-Id: I8f8e79f3442ef76268f60a8e61d2c36aedb1ccc1
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2017-03-30 20:22:36 -07:00
Greg Tucker
1268a57a32 raid: Add base function aliases and group src by arch
Change-Id: If7d987bcebb0ed1293d6836cd038746e7b0bbd85
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2017-03-30 18:09:32 -07:00
Greg Tucker
d6c5e9620d Add raid unit
New raid unit adds source for optimized xor and P+Q functions.

Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2016-04-26 15:58:49 -07:00