generic-library/isa-l
1
0
Fork 0
mirror of https://github.com/intel/isa-l.git synced 2025-01-05 22:59:52 +01:00
Code Issues Projects Releases Wiki Activity
672 Commits 6 Branches 18 Tags 6.8 MiB
37005a00fc
Commit Graph

3 Commits

Author SHA1 Message Date
Taiju Yamada
1187583a97 Fixes for aarch64 mac 
- It should be fine to enable pmull always on Apple Silicon
- macOS 12+ is required for PMULL instruction.
- Changed the conditional macro to __APPLE__
- Rewritten dispatcher using sysctlbyname
- Use __USER_LABEL_PREFIX__
- Use __TEXT,__const as readonly section
- use ASM_DEF_RODATA macro
- fix func decl

Change-Id: I800593f21085d8187b480c8bb3ab2bd70c4a6974
Signed-off-by: Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>
 2022-10-28 08:27:26 -07:00
Hang Li
02a86dfb3f erasure_code: modify eor way in aarch64 neon codes 
Change-Id: I9fb9219c5f280ed88194ec63234af046a5a036ae
Signed-off-by: Hang Li <lihang48@hisilicon.com>
 2019-11-01 15:31:33 -07:00
Zhou Xiong
d7848c1d05 Implement aarch64 neon for erasure code. 
1.Replace below erasure code interfaces to arm neon interface by mbin_interface function.
	ec_encode_data
	gf_vect_mul
	gf_vect_dot_prod
	gf_vect_mad
	ec_encode_data_update

2.Utilise arm neon instrution to accelerate GF(2^8) set compute by 128bit registor.

Change-Id: Ib0ecbfbd1837d2b1f823d26815c896724d2d22e4
Signed-off-by: Zhou Xiong <zhouxiong13@huawei.com>
 2019-10-25 11:09:03 -07:00