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3 Commits

Author SHA1 Message Date
Pablo de Lara
b8d5633e51 erasure_code: check for size alignment on powerpc gf_vect_mul_vsx implementation 
Follows the rest of the gf_vect_mul implementations for other architectures,
and checks for size alignment, stated in the documentation.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
 2024-01-15 15:48:14 +00:00
Pablo de Lara
455fdded4e erasure_code: add missing aarch64 and powerpc interface for ec_init_tables 
ec_init_tables is now a multi-implementation function,
so it requires a dispatcher for all architectures.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
 2024-01-09 13:38:43 +00:00
Hong Bo Peng
180c74aefd enable VSX SIMD in ISA-L for ppc64le 
1) Implement the ErasureCode function in Altivec Intrinsics
  2) Coding style update

Change-Id: I2c81d035f4083e9b011dbf3b741f628813b68606
Thanks-to: Daniel Axtens <dja@axtens.net>
Signed-off-by: Hong Bo Peng <penghb@cn.ibm.com>
 2020-02-20 09:40:43 -07:00