4 Commits

Author SHA1 Message Date
sunyuechi
4174804684 riscv64_multibinary support more args
Signed-off-by: sunyuechi <sunyuechi@iscas.ac.cn>
2025-05-01 17:44:19 +01:00
sunyuechi
b725bddd05 license: correct name to "ISCAS"
Signed-off-by: sunyuechi <sunyuechi@iscas.ac.cn>
2025-04-29 12:16:00 +00:00
Mattias Ellert
7e01b2c812 Address type mismatch warnings on riscv64
The riscv64 dispatcher code uses the same PROVIDER_INFO macro as the
aarch64 dispatcher and have the same kind of warnings during compilation:

igzip/riscv64/igzip_multibinary_riscv64_dispatcher.c:39:24: warning: type of 'adler32_base' does not match original declaration [-Wlto-type-mismatch]
   39 |                 return PROVIDER_BASIC(adler32);
      |                        ^
igzip/adler32_base.c:34:1: note: return value type mismatch
   34 | adler32_base(uint32_t adler32, uint8_t *start, uint64_t length)
      | ^
igzip/adler32_base.c:34:1: note: type 'uint32_t' should match type 'void'
igzip/adler32_base.c:34:1: note: 'adler32_base' was previously declared here

This commit introduces the same correction for riscv64.

Signed-off-by: Mattias Ellert <mattias.ellert@physics.uu.se>
2025-04-23 20:04:05 +01:00
sunyuechi
83d58b856c multibinary: Add run-time cpu feature detect for riscv64
Signed-off-by: sunyuechi <sunyuechi@iscas.ac.cn>
2025-03-20 19:22:40 +00:00