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igzip: Implement deflate body/finish with assembly
Change-Id: I556af7976294f31abd72ac49366f7259e3baf399 Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>
This commit is contained in:
Jerry Yu
Greg Tucker
parent
fae4c3a499
commit
f3bb041799
@ -43,6 +43,8 @@ lsrc_aarch64 += igzip/aarch64/igzip_inflate_multibinary_arm64.S \
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igzip/aarch64/igzip_multibinary_arm64.S \
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igzip/aarch64/igzip_multibinary_arm64.S \
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igzip/aarch64/igzip_isal_adler32_neon.S \
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igzip/aarch64/igzip_isal_adler32_neon.S \
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igzip/aarch64/igzip_multibinary_aarch64_dispatcher.c \
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igzip/aarch64/igzip_multibinary_aarch64_dispatcher.c \
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igzip/aarch64/igzip_deflate_body_aarch64.S \
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igzip/aarch64/igzip_deflate_finish_aarch64.S \
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igzip/proc_heap_base.c
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igzip/proc_heap_base.c
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lsrc_x86_64 += igzip/igzip_body.asm \
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lsrc_x86_64 += igzip/igzip_body.asm \
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57
igzip/aarch64/bitbuf2_aarch64.h
Normal file
57
igzip/aarch64/bitbuf2_aarch64.h
Normal file
@ -0,0 +1,57 @@
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/**********************************************************************
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Copyright(c) 2019 Arm Corporation All rights reserved.
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|
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Redistribution and use in source and binary forms, with or without
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|
modification, are permitted provided that the following conditions
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|
are met:
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||||||
|
* Redistributions of source code must retain the above copyright
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||||||
|
notice, this list of conditions and the following disclaimer.
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||||||
|
* Redistributions in binary form must reproduce the above copyright
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||||||
|
notice, this list of conditions and the following disclaimer in
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|
the documentation and/or other materials provided with the
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||||||
|
distribution.
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|
* Neither the name of Arm Corporation nor the names of its
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|
contributors may be used to endorse or promote products derived
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|
from this software without specific prior written permission.
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||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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|
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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||||||
|
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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||||||
|
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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||||||
|
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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||||||
|
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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||||||
|
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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|
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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|
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**********************************************************************/
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#ifndef __BITBUF2_AARCH64_H__
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#define __BITBUF2_AARCH64_H__
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#include "options_aarch64.h"
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#ifdef __ASSEMBLY__
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.macro update_bits stream:req,code:req,code_len:req,m_bits:req,m_bit_count:req \
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m_out_buf:req
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lsl x_\code,x_\code,x_\m_bit_count
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orr x_\m_bits,x_\code,x_\m_bits
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add x_\m_bit_count,x_\code_len,x_\m_bit_count
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str x_\m_bits,[x_\m_out_buf]
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and w_\code,w_\m_bit_count,-8
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lsr w_\code_len,w_\m_bit_count,3
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add x_\m_out_buf,x_\m_out_buf,w_\code_len,uxtw
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sub w_\m_bit_count,w_\m_bit_count,w_\code
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lsr x_\m_bits,x_\m_bits,x_\code
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str x_\m_bits,[stream,_internal_state_bitbuf_m_bits]
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str w_\m_bit_count,[stream,_internal_state_bitbuf_m_bit_count]
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str x_\m_out_buf,[stream,_internal_state_bitbuf_m_out_buf]
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.endm
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#endif
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#endif
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226
igzip/aarch64/data_struct_aarch64.h
Normal file
226
igzip/aarch64/data_struct_aarch64.h
Normal file
@ -0,0 +1,226 @@
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/**********************************************************************
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Copyright(c) 2019 Arm Corporation All rights reserved.
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|
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Redistribution and use in source and binary forms, with or without
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|
modification, are permitted provided that the following conditions
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|
are met:
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||||||
|
* Redistributions of source code must retain the above copyright
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||||||
|
notice, this list of conditions and the following disclaimer.
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||||||
|
* Redistributions in binary form must reproduce the above copyright
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||||||
|
notice, this list of conditions and the following disclaimer in
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|
the documentation and/or other materials provided with the
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||||||
|
distribution.
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|
* Neither the name of Arm Corporation nor the names of its
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|
contributors may be used to endorse or promote products derived
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||||||
|
from this software without specific prior written permission.
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||||||
|
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||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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|
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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||||||
|
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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||||||
|
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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|
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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|
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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|
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**********************************************************************/
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#ifndef __AARCH64_DATA_STRUCT_H__
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#define __AARCH64_DATA_STRUCT_H__
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#ifdef __ASSEMBLY__
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#define FIELD(name,size,align) \
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.set _FIELD_OFFSET,(_FIELD_OFFSET + (align) - 1) & (~ ((align)-1)); \
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.equ name,_FIELD_OFFSET ; \
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.set _FIELD_OFFSET,_FIELD_OFFSET + size; \
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.if align > _STRUCT_ALIGN; \
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.set _STRUCT_ALIGN, align; \
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.endif;
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#define START_STRUCT(name) .set _FIELD_OFFSET,0;.set _STRUCT_ALIGN,0;
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#define END_STRUCT(name) .set _##name##_size,_FIELD_OFFSET;\
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.set _##name##_align,_STRUCT_ALIGN
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#define CONST(name,value) .equ name,value
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/// BitBuf2
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START_STRUCT(BitBuf2)
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/// name size align
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FIELD ( _m_bits, 8, 8 )
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FIELD ( _m_bit_count, 4, 4 )
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FIELD ( _m_out_buf, 8, 8 )
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FIELD ( _m_out_end, 8, 8 )
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FIELD ( _m_out_start, 8, 8 )
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END_STRUCT(BitBuf2)
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/// isal_mod_hist
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#define HIST_ELEM_SIZE 4
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START_STRUCT(isal_mod_hist)
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/// name size align
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FIELD ( _d_hist, 30*HIST_ELEM_SIZE, HIST_ELEM_SIZE )
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FIELD ( _ll_hist, 513*HIST_ELEM_SIZE, HIST_ELEM_SIZE )
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END_STRUCT(isal_mod_hist)
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/// hufftables_icf
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#define HUFF_CODE_SIZE 4
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START_STRUCT(hufftables_icf)
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/// name size align
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FIELD ( _dist_table, 31 * HUFF_CODE_SIZE, HUFF_CODE_SIZE )
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FIELD ( _lit_len_table, 513 * HUFF_CODE_SIZE, HUFF_CODE_SIZE )
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END_STRUCT(hufftables_icf)
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/// hash8k_buf
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START_STRUCT(hash8k_buf)
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/// name size align
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FIELD ( _hash8k_table, 2 * IGZIP_HASH8K_HASH_SIZE, 2 )
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END_STRUCT(hash8k_buf)
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/// hash_map_buf
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START_STRUCT(hash_map_buf)
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/// name size align
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FIELD ( _hash_table, 2 * IGZIP_HASH_MAP_HASH_SIZE, 2 )
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FIELD ( _matches_next, 8, 8 )
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FIELD ( _matches_end, 8, 8 )
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FIELD ( _matches, 4*4*1024, 4 )
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FIELD ( _overflow, 4*LA, 4 )
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END_STRUCT(hash_map_buf)
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/// level_buf
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#define DEF_MAX_HDR_SIZE 328
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START_STRUCT(level_buf)
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/// name size align
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FIELD ( _encode_tables, _hufftables_icf_size, _hufftables_icf_align )
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FIELD ( _hist, _isal_mod_hist_size, _isal_mod_hist_align )
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FIELD ( _deflate_hdr_count, 4, 4 )
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FIELD ( _deflate_hdr_extra_bits,4, 4 )
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FIELD ( _deflate_hdr, DEF_MAX_HDR_SIZE, 1 )
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FIELD ( _icf_buf_next, 8, 8 )
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FIELD ( _icf_buf_avail_out, 8, 8 )
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FIELD ( _icf_buf_start, 8, 8 )
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FIELD ( _lvl_extra, _hash_map_buf_size, _hash_map_buf_align )
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END_STRUCT(level_buf)
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CONST( _hash8k_hash_table , _lvl_extra + _hash8k_table )
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CONST( _hash_map_hash_table , _lvl_extra + _hash_table )
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CONST( _hash_map_matches_next , _lvl_extra + _matches_next )
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CONST( _hash_map_matches_end , _lvl_extra + _matches_end )
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CONST( _hash_map_matches , _lvl_extra + _matches )
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CONST( _hist_lit_len , _hist+_ll_hist )
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CONST( _hist_dist , _hist+_d_hist )
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/// isal_zstate
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START_STRUCT(isal_zstate)
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/// name size align
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FIELD ( _total_in_start,4, 4 )
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FIELD ( _block_next, 4, 4 )
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FIELD ( _block_end, 4, 4 )
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FIELD ( _dist_mask, 4, 4 )
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FIELD ( _hash_mask, 4, 4 )
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FIELD ( _state, 4, 4 )
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FIELD ( _bitbuf, _BitBuf2_size, _BitBuf2_align )
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FIELD ( _crc, 4, 4 )
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FIELD ( _has_wrap_hdr, 1, 1 )
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FIELD ( _has_eob_hdr, 1, 1 )
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FIELD ( _has_eob, 1, 1 )
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FIELD ( _has_hist, 1, 1 )
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FIELD ( _has_level_buf_init, 2, 2 )
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FIELD ( _count, 4, 4 )
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FIELD ( _tmp_out_buff, 16, 1 )
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FIELD ( _tmp_out_start, 4, 4 )
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FIELD ( _tmp_out_end, 4, 4 )
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FIELD ( _b_bytes_valid, 4, 4 )
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FIELD ( _b_bytes_processed, 4, 4 )
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FIELD ( _buffer, BSIZE, 1 )
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FIELD ( _head, IGZIP_LVL0_HASH_SIZE*2, 2 )
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END_STRUCT(isal_zstate)
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CONST( _bitbuf_m_bits , _bitbuf+_m_bits )
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CONST( _bitbuf_m_bit_count , _bitbuf+_m_bit_count )
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CONST( _bitbuf_m_out_buf , _bitbuf+_m_out_buf )
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CONST( _bitbuf_m_out_end , _bitbuf+_m_out_end )
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CONST( _bitbuf_m_out_start , _bitbuf+_m_out_start )
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/// isal_zstream
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START_STRUCT(isal_zstream)
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/// name size align
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FIELD ( _next_in, 8, 8 )
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FIELD ( _avail_in, 4, 4 )
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FIELD ( _total_in, 4, 4 )
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FIELD ( _next_out, 8, 8 )
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FIELD ( _avail_out, 4, 4 )
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FIELD ( _total_out, 4, 4 )
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FIELD ( _hufftables, 8, 8 )
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FIELD ( _level, 4, 4 )
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FIELD ( _level_buf_size, 4, 4 )
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FIELD ( _level_buf, 8, 8 )
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FIELD ( _end_of_stream, 2, 2 )
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FIELD ( _flush, 2, 2 )
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FIELD ( _gzip_flag, 2, 2 )
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FIELD ( _hist_bits, 2, 2 )
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FIELD ( _internal_state, _isal_zstate_size, _isal_zstate_align )
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END_STRUCT(isal_zstream)
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CONST( _internal_state_total_in_start , _internal_state+_total_in_start )
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CONST( _internal_state_block_next , _internal_state+_block_next )
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CONST( _internal_state_block_end , _internal_state+_block_end )
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CONST( _internal_state_b_bytes_valid , _internal_state+_b_bytes_valid )
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CONST( _internal_state_b_bytes_processed , _internal_state+_b_bytes_processed )
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CONST( _internal_state_crc , _internal_state+_crc )
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CONST( _internal_state_dist_mask , _internal_state+_dist_mask )
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CONST( _internal_state_hash_mask , _internal_state+_hash_mask )
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CONST( _internal_state_bitbuf , _internal_state+_bitbuf )
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CONST( _internal_state_state , _internal_state+_state )
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CONST( _internal_state_count , _internal_state+_count )
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CONST( _internal_state_tmp_out_buff , _internal_state+_tmp_out_buff )
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CONST( _internal_state_tmp_out_start , _internal_state+_tmp_out_start )
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CONST( _internal_state_tmp_out_end , _internal_state+_tmp_out_end )
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CONST( _internal_state_has_wrap_hdr , _internal_state+_has_wrap_hdr )
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CONST( _internal_state_has_eob , _internal_state+_has_eob )
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CONST( _internal_state_has_eob_hdr , _internal_state+_has_eob_hdr )
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CONST( _internal_state_has_hist , _internal_state+_has_hist )
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CONST( _internal_state_has_level_buf_init , _internal_state+_has_level_buf_init )
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CONST( _internal_state_buffer , _internal_state+_buffer )
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CONST( _internal_state_head , _internal_state+_head )
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CONST( _internal_state_bitbuf_m_bits , _internal_state+_bitbuf_m_bits )
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CONST( _internal_state_bitbuf_m_bit_count , _internal_state+_bitbuf_m_bit_count )
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CONST( _internal_state_bitbuf_m_out_buf , _internal_state+_bitbuf_m_out_buf )
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CONST( _internal_state_bitbuf_m_out_end , _internal_state+_bitbuf_m_out_end )
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CONST( _internal_state_bitbuf_m_out_start , _internal_state+_bitbuf_m_out_start )
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/// Internal States
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CONST( ZSTATE_NEW_HDR , 0 )
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CONST( ZSTATE_HDR , (ZSTATE_NEW_HDR + 1) )
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CONST( ZSTATE_CREATE_HDR , (ZSTATE_HDR + 1) )
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CONST( ZSTATE_BODY , (ZSTATE_CREATE_HDR + 1) )
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CONST( ZSTATE_FLUSH_READ_BUFFER , (ZSTATE_BODY + 1) )
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CONST( ZSTATE_FLUSH_ICF_BUFFER , (ZSTATE_FLUSH_READ_BUFFER + 1) )
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CONST( ZSTATE_TYPE0_HDR , (ZSTATE_FLUSH_ICF_BUFFER + 1) )
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CONST( ZSTATE_TYPE0_BODY , (ZSTATE_TYPE0_HDR + 1) )
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CONST( ZSTATE_SYNC_FLUSH , (ZSTATE_TYPE0_BODY + 1) )
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CONST( ZSTATE_FLUSH_WRITE_BUFFER , (ZSTATE_SYNC_FLUSH + 1) )
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CONST( ZSTATE_TRL , (ZSTATE_FLUSH_WRITE_BUFFER + 1) )
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CONST( _NO_FLUSH , 0 )
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CONST( _SYNC_FLUSH , 1 )
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CONST( _FULL_FLUSH , 2 )
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CONST( _STORED_BLK , 0 )
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CONST( IGZIP_NO_HIST , 0 )
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CONST( IGZIP_HIST , 1 )
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CONST( IGZIP_DICT_HIST , 2 )
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#endif
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#endif
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154
igzip/aarch64/huffman_aarch64.h
Normal file
154
igzip/aarch64/huffman_aarch64.h
Normal file
@ -0,0 +1,154 @@
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/**********************************************************************
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Copyright(c) 2019 Arm Corporation All rights reserved.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without
|
||||||
|
modification, are permitted provided that the following conditions
|
||||||
|
are met:
|
||||||
|
* Redistributions of source code must retain the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer.
|
||||||
|
* Redistributions in binary form must reproduce the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer in
|
||||||
|
the documentation and/or other materials provided with the
|
||||||
|
distribution.
|
||||||
|
* Neither the name of Arm Corporation nor the names of its
|
||||||
|
contributors may be used to endorse or promote products derived
|
||||||
|
from this software without specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
**********************************************************************/
|
||||||
|
|
||||||
|
#ifndef __HUFFMAN_AARCH64_H__
|
||||||
|
#define __HUFFMAN_AARCH64_H__
|
||||||
|
|
||||||
|
#ifdef __ASSEMBLY__
|
||||||
|
#ifdef LONGER_HUFFTABLE
|
||||||
|
#if (D > 8192)
|
||||||
|
#error History D is larger than 8K
|
||||||
|
#else
|
||||||
|
#define DIST_TABLE_SIZE 8192
|
||||||
|
#define DECODE_OFFSET 26
|
||||||
|
#endif
|
||||||
|
#else
|
||||||
|
#define DIST_TABLE_SIZE 2
|
||||||
|
#define DECODE_OFFSET 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define LEN_TABLE_SIZE 256
|
||||||
|
#define LIT_TABLE_SIZE 257
|
||||||
|
|
||||||
|
#define DIST_TABLE_START (ISAL_DEF_MAX_HDR_SIZE + 8) //328+8
|
||||||
|
#define DIST_TABLE_OFFSET (DIST_TABLE_START + - 4 * 1) //336-4
|
||||||
|
#define LEN_TABLE_OFFSET (DIST_TABLE_START + DIST_TABLE_SIZE * 4 - 4*3) //332 + 2*4 -4*3 =328
|
||||||
|
#define LIT_TABLE_OFFSET (DIST_TABLE_START + 4 * DIST_TABLE_SIZE + 4 * LEN_TABLE_SIZE)
|
||||||
|
#define LIT_TABLE_SIZES_OFFSET (LIT_TABLE_OFFSET + 2 * LIT_TABLE_SIZE)
|
||||||
|
#define DCODE_TABLE_OFFSET (LIT_TABLE_SIZES_OFFSET + LIT_TABLE_SIZE + 1 - DECODE_OFFSET * 2)
|
||||||
|
#define DCODE_TABLE_SIZE_OFFSET (DCODE_TABLE_OFFSET + 2 * 30 - DECODE_OFFSET)
|
||||||
|
|
||||||
|
#define IGZIP_DECODE_OFFSET 0
|
||||||
|
#define IGZIP_DIST_TABLE_SIZE 2
|
||||||
|
|
||||||
|
.macro get_len_code hufftables:req,length:req,code:req,code_len:req,tmp0:req
|
||||||
|
add x_\tmp0,\hufftables,LEN_TABLE_OFFSET
|
||||||
|
ldr w_\code_len,[x_\tmp0,x_\length,lsl 2]
|
||||||
|
lsr w_\code, w_\code_len , 5
|
||||||
|
and x_\code_len,x_\code_len,0x1f
|
||||||
|
.endm
|
||||||
|
|
||||||
|
.macro get_lit_code hufftables:req,lit:req,code:req,code_len:req
|
||||||
|
add x_\code,\hufftables,LIT_TABLE_OFFSET
|
||||||
|
ldrh w_\code,[x_\code,x_\lit,lsl 1]
|
||||||
|
add x_\code_len,\hufftables,LIT_TABLE_SIZES_OFFSET
|
||||||
|
ldrb w_\code_len,[x_\code_len,x_\lit]
|
||||||
|
.endm
|
||||||
|
|
||||||
|
.macro get_dist_code hufftables:req,dist:req,code:req,code_len:req,tmp0:req,tmp1:req,tmp2:req
|
||||||
|
cmp dist,DIST_TABLE_SIZE
|
||||||
|
bhi _compute_dist_code
|
||||||
|
add x_\tmp0,\hufftables,DIST_TABLE_OFFSET
|
||||||
|
ldr w_\code_len,[x_\tmp0,x_\dist,lsl 2]
|
||||||
|
lsr w_\code, w_\code_len , 5
|
||||||
|
and x_\code_len,x_\code_len,0x1f
|
||||||
|
b _end_get_dist_code
|
||||||
|
_compute_dist_code:
|
||||||
|
and w_\dist,w_\dist,0xffff
|
||||||
|
sub w_\dist,w_\dist,1
|
||||||
|
clz w_\tmp0,w_\dist
|
||||||
|
mov w_\tmp1,30
|
||||||
|
sub w_\tmp0,w_\tmp1,w_\tmp0 //tmp0== num_extra_bists
|
||||||
|
mov w_\tmp1,1
|
||||||
|
lsl w_\tmp1,w_\tmp1,w_\tmp0
|
||||||
|
sub w_\tmp1,w_\tmp1,1
|
||||||
|
and w_\tmp1,w_\tmp1,w_\dist //tmp1=extra_bits
|
||||||
|
asr w_\dist,w_\dist,w_\tmp0
|
||||||
|
lsl w_\tmp2,w_\tmp0,1
|
||||||
|
add w_\tmp2,w_\dist,w_\tmp2 //tmp2=sym
|
||||||
|
|
||||||
|
add x_\code,\hufftables,DCODE_TABLE_OFFSET - IGZIP_DECODE_OFFSET*2
|
||||||
|
add x_\code_len,\hufftables,DCODE_TABLE_SIZE_OFFSET - IGZIP_DECODE_OFFSET
|
||||||
|
ldrh w_\code,[x_\code,x_\tmp2,lsl 1]
|
||||||
|
ldrb w_\code_len,[x_\code_len,x_\tmp2]
|
||||||
|
lsl w_\tmp1,w_\tmp1,w_\code_len
|
||||||
|
orr w_\code,w_\code,w_\tmp1
|
||||||
|
add w_\code_len,w_\code_len,w_\tmp0
|
||||||
|
|
||||||
|
//compute_dist_code
|
||||||
|
_end_get_dist_code:
|
||||||
|
.endm
|
||||||
|
|
||||||
|
|
||||||
|
.macro compare_258_bytes str0:req,str1:req,match_length:req,tmp0:req,tmp1:req
|
||||||
|
mov x_\match_length,0
|
||||||
|
_compare_258_loop:
|
||||||
|
ldr x_\tmp0,[x_\str0,x_\match_length]
|
||||||
|
ldr x_\tmp1,[x_\str1,x_\match_length]
|
||||||
|
eor x_\tmp0,x_\tmp1,x_\tmp0
|
||||||
|
rbit x_\tmp0,x_\tmp0
|
||||||
|
clz x_\tmp0,x_\tmp0
|
||||||
|
lsr x_\tmp0,x_\tmp0,3
|
||||||
|
add x_\match_length,x_\match_length,x_\tmp0
|
||||||
|
|
||||||
|
|
||||||
|
cmp x_\match_length,257
|
||||||
|
ccmp x_\tmp0,8,0,ls
|
||||||
|
beq _compare_258_loop
|
||||||
|
|
||||||
|
cmp x_\match_length,258
|
||||||
|
mov x_\tmp1,258
|
||||||
|
csel x_\match_length,x_\match_length,x_\tmp1,ls
|
||||||
|
.endm
|
||||||
|
|
||||||
|
.macro compare_max_258_bytes str0:req,str1:req,max_length:req,match_length:req,tmp0:req,tmp1:req
|
||||||
|
mov x_\match_length,0
|
||||||
|
mov x_\tmp0,258
|
||||||
|
cmp x_\max_length,x_\tmp0
|
||||||
|
csel x_\max_length,x_\max_length,x_\tmp0,ls
|
||||||
|
_compare_258_loop:
|
||||||
|
ldr x_\tmp0,[x_\str0,x_\match_length]
|
||||||
|
ldr x_\tmp1,[x_\str1,x_\match_length]
|
||||||
|
eor x_\tmp0,x_\tmp1,x_\tmp0
|
||||||
|
rbit x_\tmp0,x_\tmp0
|
||||||
|
clz x_\tmp0,x_\tmp0
|
||||||
|
lsr x_\tmp0,x_\tmp0,3
|
||||||
|
add x_\match_length,x_\match_length,x_\tmp0
|
||||||
|
|
||||||
|
|
||||||
|
cmp x_\max_length,x_\match_length
|
||||||
|
ccmp x_\tmp0,8,0,hi
|
||||||
|
beq _compare_258_loop
|
||||||
|
|
||||||
|
cmp x_\match_length,x_\max_length
|
||||||
|
csel x_\match_length,x_\match_length,x_\max_length,ls
|
||||||
|
.endm
|
||||||
|
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
261
igzip/aarch64/igzip_deflate_body_aarch64.S
Normal file
261
igzip/aarch64/igzip_deflate_body_aarch64.S
Normal file
@ -0,0 +1,261 @@
|
|||||||
|
/**********************************************************************
|
||||||
|
Copyright(c) 2019 Arm Corporation All rights reserved.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without
|
||||||
|
modification, are permitted provided that the following conditions
|
||||||
|
are met:
|
||||||
|
* Redistributions of source code must retain the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer.
|
||||||
|
* Redistributions in binary form must reproduce the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer in
|
||||||
|
the documentation and/or other materials provided with the
|
||||||
|
distribution.
|
||||||
|
* Neither the name of Arm Corporation nor the names of its
|
||||||
|
contributors may be used to endorse or promote products derived
|
||||||
|
from this software without specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
**********************************************************************/
|
||||||
|
.arch armv8-a+crc
|
||||||
|
.text
|
||||||
|
.align 2
|
||||||
|
#include "lz0a_const_aarch64.h"
|
||||||
|
#include "data_struct_aarch64.h"
|
||||||
|
#include "huffman_aarch64.h"
|
||||||
|
#include "bitbuf2_aarch64.h"
|
||||||
|
#include "stdmac_aarch64.h"
|
||||||
|
/*
|
||||||
|
declare Macros
|
||||||
|
*/
|
||||||
|
|
||||||
|
.macro declare_generic_reg name:req,reg:req,default:req
|
||||||
|
\name .req \default\reg
|
||||||
|
w_\name .req w\reg
|
||||||
|
x_\name .req x\reg
|
||||||
|
.endm
|
||||||
|
|
||||||
|
.macro update_state stream:req,start_in:req,next_in:req,end_in:req, \
|
||||||
|
m_out_buf:req,m_out_start:req,tmp0:req,tmp1:req
|
||||||
|
|
||||||
|
//m_out_buf=bytes_written
|
||||||
|
sub x_\m_out_buf,x_\m_out_buf,x_\m_out_start
|
||||||
|
cmp next_in,start_in
|
||||||
|
bls skip_has_hist
|
||||||
|
mov w_\tmp0,1
|
||||||
|
strb w_\tmp0,[x_\stream,_internal_state_has_hist]
|
||||||
|
skip_has_hist:
|
||||||
|
ldr w_\tmp0,[\stream,_total_in]
|
||||||
|
ldr x_\m_out_start,[\stream,_next_out] //m_out_start = next_out
|
||||||
|
|
||||||
|
str x_\next_in,[\stream,_next_in]
|
||||||
|
sub x_\start_in,x_\next_in,x_\start_in
|
||||||
|
sub x_\end_in,x_\end_in,x_\next_in
|
||||||
|
add w_\tmp0,w_\tmp0,w_\start_in
|
||||||
|
stp w_\end_in,w_\tmp0,[\stream,_avail_in]
|
||||||
|
//next_in=avail_out,start_in=total_out
|
||||||
|
ldp w_\next_in,w_\start_in,[\stream,_avail_out]
|
||||||
|
add x_\m_out_start,x_\m_out_start,x_\m_out_buf
|
||||||
|
str x_\m_out_start,[\stream,_next_out]
|
||||||
|
add w_\start_in,w_\start_in,w_\m_out_buf
|
||||||
|
sub w_\next_in,w_\next_in,w_\m_out_buf
|
||||||
|
stp w_\next_in,w_\start_in,[\stream,_avail_out]
|
||||||
|
.endm
|
||||||
|
|
||||||
|
|
||||||
|
.global isal_deflate_body_aarch64
|
||||||
|
.type isal_deflate_body_aarch64, %function
|
||||||
|
/*
|
||||||
|
void isal_deflate_body_aarch64(struct isal_zstream *stream)
|
||||||
|
*/
|
||||||
|
declare_generic_reg stream, 0,x //struct isal_zstream *stream
|
||||||
|
declare_generic_reg state, 8,x //&stream->state
|
||||||
|
declare_generic_reg avail_in, 9,w
|
||||||
|
declare_generic_reg end_of_stream, 10,w //can be used in loop
|
||||||
|
|
||||||
|
declare_generic_reg hash_mask, 11,w
|
||||||
|
declare_generic_reg match_length, 12,w
|
||||||
|
declare_generic_reg hufftables, 13,x
|
||||||
|
|
||||||
|
declare_generic_reg m_out_buf, 14,x
|
||||||
|
declare_generic_reg m_out_start, 15,x
|
||||||
|
declare_generic_reg m_out_end, 16,x
|
||||||
|
declare_generic_reg m_bits, 17,x
|
||||||
|
declare_generic_reg m_bit_count, 18,w
|
||||||
|
|
||||||
|
declare_generic_reg start_in, 19,x
|
||||||
|
declare_generic_reg end_in, 20,x
|
||||||
|
declare_generic_reg next_in, 21,x
|
||||||
|
declare_generic_reg loop_end_cnt, 22,x
|
||||||
|
|
||||||
|
declare_generic_reg literal, 23,w
|
||||||
|
declare_generic_reg hash, 24,w
|
||||||
|
declare_generic_reg dist, 25,w
|
||||||
|
|
||||||
|
declare_generic_reg last_seen, 26,x
|
||||||
|
declare_generic_reg file_start, 27,x
|
||||||
|
declare_generic_reg hist_size, 28,w
|
||||||
|
|
||||||
|
declare_generic_reg tmp0, 5 ,w
|
||||||
|
declare_generic_reg tmp1, 6 ,w
|
||||||
|
declare_generic_reg tmp2, 7 ,w
|
||||||
|
|
||||||
|
declare_generic_reg code, 3,x
|
||||||
|
declare_generic_reg code_len, 24,x
|
||||||
|
declare_generic_reg code2, 10,x
|
||||||
|
declare_generic_reg code_len2, 4,x
|
||||||
|
|
||||||
|
|
||||||
|
isal_deflate_body_aarch64:
|
||||||
|
//save registers
|
||||||
|
push_stack
|
||||||
|
ldr avail_in, [stream, _avail_in]
|
||||||
|
cbz avail_in, exit_save_state
|
||||||
|
|
||||||
|
// set_buf(&state->bitbuf, stream->next_out, stream->avail_out);
|
||||||
|
ldr w_m_out_end,[stream,_avail_out]
|
||||||
|
ldr m_out_buf,[stream,_next_out]
|
||||||
|
add m_out_end,m_out_buf,w_m_out_end,uxtw
|
||||||
|
sub m_out_end,m_out_end , 8
|
||||||
|
mov m_out_start,m_out_buf
|
||||||
|
stp m_out_buf,m_out_end,[stream, _bitbuf + _internal_state + _m_out_buf]
|
||||||
|
str m_out_start,[stream, _bitbuf + _internal_state + _m_out_start]
|
||||||
|
ldr m_bit_count ,[stream,_internal_state_bitbuf_m_bit_count]
|
||||||
|
ldr m_bits ,[stream,_internal_state_bitbuf_m_bits]
|
||||||
|
|
||||||
|
|
||||||
|
//init variables
|
||||||
|
//last_seen=&stream.internal_state.head = _internal_state+_head
|
||||||
|
add last_seen,stream,65536
|
||||||
|
add last_seen,last_seen,_internal_state+_head -65536
|
||||||
|
|
||||||
|
|
||||||
|
//start_in=stream->next_in;next_in=start_in
|
||||||
|
ldr start_in,[stream,_next_in]
|
||||||
|
mov next_in,start_in
|
||||||
|
add end_in,start_in,avail_in,uxtw //avail_in reg is free now
|
||||||
|
sub loop_end_cnt,end_in,289 //loop end
|
||||||
|
cmp next_in,loop_end_cnt
|
||||||
|
|
||||||
|
|
||||||
|
//file_start = (uint8_t *) ((uintptr_t) stream->next_in - stream->total_in);
|
||||||
|
ldr w_file_start,[stream,_total_in]
|
||||||
|
sub file_start,next_in,file_start,uxtw
|
||||||
|
|
||||||
|
//uint32_t hist_size = state->dist_mask;
|
||||||
|
ldr hist_size,[stream,_internal_state + _dist_mask]
|
||||||
|
|
||||||
|
//uint32_t hash_mask = state->hash_mask;
|
||||||
|
ldr hash_mask,[stream,_internal_state + _hash_mask]
|
||||||
|
|
||||||
|
ldr hufftables,[stream,_hufftables]
|
||||||
|
|
||||||
|
bhi main_loop_end
|
||||||
|
main_loop_start:
|
||||||
|
//is_full(&state->bitbuf)
|
||||||
|
cmp m_out_buf,m_out_end
|
||||||
|
bhi update_state_exit
|
||||||
|
|
||||||
|
ldr literal,[next_in]
|
||||||
|
crc32cw hash,wzr,literal
|
||||||
|
and hash,hash,hash_mask
|
||||||
|
|
||||||
|
///dist = (next_in - file_start - last_seen[hash]) & 0xFFFF;
|
||||||
|
ldrh w_tmp0,[last_seen,x_hash,lsl 1] //tmp_w last_seen[hash]
|
||||||
|
sub x_dist,next_in,file_start
|
||||||
|
//last_seen[hash] = (uint64_t) (next_in - file_start);
|
||||||
|
strh dist,[last_seen,x_hash,lsl 1]
|
||||||
|
sub dist,dist,w_tmp0
|
||||||
|
and dist,dist,0xffff
|
||||||
|
|
||||||
|
sub w_tmp0,dist,1
|
||||||
|
cmp hist_size,w_tmp0
|
||||||
|
bls get_lit_code
|
||||||
|
|
||||||
|
///match_length = compare258(next_in - dist, next_in, 258);
|
||||||
|
sub x_tmp2,next_in,x_dist
|
||||||
|
compare_258_bytes tmp2,next_in,match_length,tmp0,tmp1
|
||||||
|
cmp match_length,3
|
||||||
|
bls get_lit_code
|
||||||
|
|
||||||
|
sub x_tmp0,next_in,file_start
|
||||||
|
ldr literal,[next_in,1]
|
||||||
|
crc32cw hash,wzr,literal
|
||||||
|
and hash,hash,hash_mask
|
||||||
|
add tmp0,tmp0,1
|
||||||
|
strh tmp0,[last_seen,x_hash,lsl 1]
|
||||||
|
//call_print_b hash,dist,last_seen
|
||||||
|
|
||||||
|
ldr literal,[next_in,2]
|
||||||
|
crc32cw hash,wzr,literal
|
||||||
|
and hash,hash,hash_mask
|
||||||
|
add tmp0,tmp0,1
|
||||||
|
strh tmp0,[last_seen,x_hash,lsl 1]
|
||||||
|
|
||||||
|
//get_len_code(stream->hufftables, match_length, &code,
|
||||||
|
// &code_len);
|
||||||
|
get_len_code hufftables,match_length,code,code_len,tmp0
|
||||||
|
|
||||||
|
//get_dist_code(stream->hufftables, dist, &code2, &code_len2);
|
||||||
|
get_dist_code hufftables,dist,code2,code_len2,tmp0,tmp1,tmp2
|
||||||
|
|
||||||
|
//code |= code2 << code_len;
|
||||||
|
//code_len += code_len2;
|
||||||
|
lsl code2,code2,code_len
|
||||||
|
orr code,code,code2
|
||||||
|
add code_len,code_len,code_len2
|
||||||
|
|
||||||
|
//next_in += match_length;
|
||||||
|
add next_in,next_in,match_length,uxtw
|
||||||
|
|
||||||
|
//write_bits(&state->bitbuf, code, code_len);
|
||||||
|
update_bits stream,code,code_len,m_bits,m_bit_count,m_out_buf
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
cmp next_in,loop_end_cnt
|
||||||
|
bls main_loop_start
|
||||||
|
b main_loop_end
|
||||||
|
get_lit_code:
|
||||||
|
//get_lit_code(stream->hufftables, literal & 0xFF, &code, &code_len);
|
||||||
|
and literal,literal,0xff
|
||||||
|
get_lit_code hufftables,literal,code,code_len
|
||||||
|
|
||||||
|
//next_in++;
|
||||||
|
add next_in,next_in,1
|
||||||
|
|
||||||
|
//write_bits(&state->bitbuf, code, code_len);
|
||||||
|
update_bits stream,code,code_len,m_bits,m_bit_count,m_out_buf
|
||||||
|
cmp next_in,loop_end_cnt
|
||||||
|
bls main_loop_start
|
||||||
|
|
||||||
|
main_loop_end:
|
||||||
|
//update state here
|
||||||
|
|
||||||
|
//load end_of_stream and flush together
|
||||||
|
ldr w_end_of_stream, [stream, _end_of_stream]
|
||||||
|
//(stream->end_of_stream || stream->flush != 0)
|
||||||
|
cbz w_end_of_stream, update_state_exit
|
||||||
|
mov w_tmp0 , ZSTATE_FLUSH_READ_BUFFER
|
||||||
|
str w_tmp0, [stream, _internal_state+_state]
|
||||||
|
update_state_exit:
|
||||||
|
update_state stream,start_in,next_in,end_in,m_out_buf,m_out_start,tmp0,tmp1
|
||||||
|
exit_ret:
|
||||||
|
pop_stack
|
||||||
|
ret
|
||||||
|
exit_save_state:
|
||||||
|
ldr w_end_of_stream, [stream, _end_of_stream]
|
||||||
|
cbz w_end_of_stream, exit_ret //(stream->end_of_stream || stream->flush != 0)
|
||||||
|
mov w_tmp0 , ZSTATE_FLUSH_READ_BUFFER
|
||||||
|
str w_tmp0, [stream, _internal_state+_state]
|
||||||
|
b exit_ret
|
||||||
|
.size isal_deflate_body_aarch64, .-isal_deflate_body_aarch64
|
||||||
264
igzip/aarch64/igzip_deflate_finish_aarch64.S
Normal file
264
igzip/aarch64/igzip_deflate_finish_aarch64.S
Normal file
@ -0,0 +1,264 @@
|
|||||||
|
/**********************************************************************
|
||||||
|
Copyright(c) 2019 Arm Corporation All rights reserved.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without
|
||||||
|
modification, are permitted provided that the following conditions
|
||||||
|
are met:
|
||||||
|
* Redistributions of source code must retain the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer.
|
||||||
|
* Redistributions in binary form must reproduce the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer in
|
||||||
|
the documentation and/or other materials provided with the
|
||||||
|
distribution.
|
||||||
|
* Neither the name of Arm Corporation nor the names of its
|
||||||
|
contributors may be used to endorse or promote products derived
|
||||||
|
from this software without specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
**********************************************************************/
|
||||||
|
.arch armv8-a+crc
|
||||||
|
.text
|
||||||
|
.align 2
|
||||||
|
|
||||||
|
#include "lz0a_const_aarch64.h"
|
||||||
|
#include "data_struct_aarch64.h"
|
||||||
|
#include "huffman_aarch64.h"
|
||||||
|
#include "bitbuf2_aarch64.h"
|
||||||
|
#include "stdmac_aarch64.h"
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
declare Macros
|
||||||
|
*/
|
||||||
|
|
||||||
|
.macro declare_generic_reg name:req,reg:req,default:req
|
||||||
|
\name .req \default\reg
|
||||||
|
w_\name .req w\reg
|
||||||
|
x_\name .req x\reg
|
||||||
|
.endm
|
||||||
|
|
||||||
|
.macro update_state stream:req,start_in:req,next_in:req,end_in:req, \
|
||||||
|
m_out_buf:req,m_out_start:req,tmp0:req,tmp1:req
|
||||||
|
|
||||||
|
//m_out_buf=bytes_written
|
||||||
|
sub x_\m_out_buf,x_\m_out_buf,x_\m_out_start
|
||||||
|
cmp next_in,start_in
|
||||||
|
bls skip_has_hist
|
||||||
|
mov w_\tmp0,1
|
||||||
|
strb w_\tmp0,[x_\stream,_internal_state_has_hist]
|
||||||
|
skip_has_hist:
|
||||||
|
ldr w_\tmp0,[\stream,_total_in]
|
||||||
|
ldr x_\m_out_start,[\stream,_next_out] //m_out_start = next_out
|
||||||
|
|
||||||
|
str x_\next_in,[\stream,_next_in]
|
||||||
|
sub x_\start_in,x_\next_in,x_\start_in
|
||||||
|
sub x_\end_in,x_\end_in,x_\next_in
|
||||||
|
add w_\tmp0,w_\tmp0,w_\start_in
|
||||||
|
stp w_\end_in,w_\tmp0,[\stream,_avail_in]
|
||||||
|
//next_in=avail_out,start_in=total_out
|
||||||
|
ldp w_\next_in,w_\start_in,[\stream,_avail_out]
|
||||||
|
add x_\m_out_start,x_\m_out_start,x_\m_out_buf
|
||||||
|
str x_\m_out_start,[\stream,_next_out]
|
||||||
|
add w_\start_in,w_\start_in,w_\m_out_buf
|
||||||
|
sub w_\next_in,w_\next_in,w_\m_out_buf
|
||||||
|
stp w_\next_in,w_\start_in,[\stream,_avail_out]
|
||||||
|
.endm
|
||||||
|
.global isal_deflate_finish_aarch64
|
||||||
|
.arch armv8-a+crc
|
||||||
|
.type isal_deflate_finish_aarch64, %function
|
||||||
|
/*
|
||||||
|
void isal_deflate_finish_aarch64(struct isal_zstream *stream)
|
||||||
|
*/
|
||||||
|
declare_generic_reg stream, 0,x //struct isal_zstream *stream
|
||||||
|
declare_generic_reg state, 8,x //&stream->state
|
||||||
|
declare_generic_reg avail_in, 9,w
|
||||||
|
declare_generic_reg end_of_stream, 10,w //can be used in loop
|
||||||
|
|
||||||
|
declare_generic_reg hash_mask, 11,w
|
||||||
|
declare_generic_reg match_length, 12,w
|
||||||
|
declare_generic_reg hufftables, 13,x
|
||||||
|
|
||||||
|
declare_generic_reg m_out_buf, 14,x
|
||||||
|
declare_generic_reg m_out_start, 15,x
|
||||||
|
declare_generic_reg m_out_end, 16,x
|
||||||
|
declare_generic_reg m_bits, 17,x
|
||||||
|
declare_generic_reg m_bit_count, 18,w
|
||||||
|
|
||||||
|
declare_generic_reg start_in, 19,x
|
||||||
|
declare_generic_reg end_in, 20,x
|
||||||
|
declare_generic_reg next_in, 21,x
|
||||||
|
declare_generic_reg loop_end_cnt, 22,x
|
||||||
|
|
||||||
|
declare_generic_reg literal, 23,w
|
||||||
|
declare_generic_reg hash, 24,w
|
||||||
|
declare_generic_reg dist, 25,w
|
||||||
|
|
||||||
|
declare_generic_reg last_seen, 26,x
|
||||||
|
declare_generic_reg file_start, 27,x
|
||||||
|
declare_generic_reg hist_size, 28,w
|
||||||
|
|
||||||
|
declare_generic_reg tmp0, 5 ,w
|
||||||
|
declare_generic_reg tmp1, 6 ,w
|
||||||
|
declare_generic_reg tmp2, 7 ,w
|
||||||
|
|
||||||
|
declare_generic_reg code, 3,x
|
||||||
|
declare_generic_reg code_len, 24,x
|
||||||
|
declare_generic_reg code2, 10,x
|
||||||
|
declare_generic_reg code_len2, 4,x
|
||||||
|
|
||||||
|
|
||||||
|
isal_deflate_finish_aarch64:
|
||||||
|
//save registers
|
||||||
|
push_stack
|
||||||
|
|
||||||
|
// set_buf(&state->bitbuf, stream->next_out, stream->avail_out);
|
||||||
|
ldr w_m_out_end,[stream,_avail_out]
|
||||||
|
ldr m_out_buf,[stream,_next_out]
|
||||||
|
add m_out_end,m_out_buf,w_m_out_end,uxtw
|
||||||
|
sub m_out_end,m_out_end , 8
|
||||||
|
mov m_out_start,m_out_buf
|
||||||
|
stp m_out_buf,m_out_end,[stream, _bitbuf + _internal_state + _m_out_buf]
|
||||||
|
str m_out_start,[stream, _bitbuf + _internal_state + _m_out_start]
|
||||||
|
ldr m_bit_count ,[stream,_internal_state_bitbuf_m_bit_count]
|
||||||
|
ldr m_bits ,[stream,_internal_state_bitbuf_m_bits]
|
||||||
|
|
||||||
|
//init variables
|
||||||
|
//last_seen=&stream.internal_state.head = _internal_state+_head
|
||||||
|
add last_seen,stream,65536
|
||||||
|
add last_seen,last_seen,_internal_state+_head -65536
|
||||||
|
|
||||||
|
|
||||||
|
//start_in=stream->next_in;next_in=start_in
|
||||||
|
ldr avail_in, [stream, _avail_in]
|
||||||
|
ldr start_in,[stream,_next_in]
|
||||||
|
mov next_in,start_in
|
||||||
|
add end_in,start_in,avail_in,uxtw //avail_in reg is free now
|
||||||
|
ldr hufftables,[stream,_hufftables]
|
||||||
|
cbz avail_in, update_not_full
|
||||||
|
|
||||||
|
|
||||||
|
sub loop_end_cnt,end_in,4 //loop end
|
||||||
|
cmp next_in,loop_end_cnt
|
||||||
|
|
||||||
|
|
||||||
|
//file_start = (uint8_t *) ((uintptr_t) stream->next_in - stream->total_in);
|
||||||
|
ldr w_file_start,[stream,_total_in]
|
||||||
|
sub file_start,next_in,file_start,uxtw
|
||||||
|
|
||||||
|
//uint32_t hist_size = state->dist_mask;
|
||||||
|
ldr hist_size,[stream,_internal_state + _dist_mask]
|
||||||
|
|
||||||
|
//uint32_t hash_mask = state->hash_mask;
|
||||||
|
ldr hash_mask,[stream,_internal_state + _hash_mask]
|
||||||
|
|
||||||
|
bhi main_loop_end
|
||||||
|
main_loop_start:
|
||||||
|
//is_full(&state->bitbuf)
|
||||||
|
cmp m_out_buf,m_out_end
|
||||||
|
bhi update_state_exit
|
||||||
|
|
||||||
|
ldr literal,[next_in]
|
||||||
|
crc32cw hash,wzr,literal
|
||||||
|
and hash,hash,hash_mask
|
||||||
|
|
||||||
|
///dist = (next_in - file_start - last_seen[hash]) & 0xFFFF;
|
||||||
|
ldrh w_tmp0,[last_seen,x_hash,lsl 1] //tmp_w last_seen[hash]
|
||||||
|
sub x_dist,next_in,file_start
|
||||||
|
//last_seen[hash] = (uint64_t) (next_in - file_start);
|
||||||
|
strh dist,[last_seen,x_hash,lsl 1]
|
||||||
|
sub dist,dist,w_tmp0
|
||||||
|
and dist,dist,0xffff
|
||||||
|
|
||||||
|
sub w_tmp0,dist,1
|
||||||
|
cmp hist_size,w_tmp0
|
||||||
|
bls get_lit_code
|
||||||
|
|
||||||
|
/// match_length = compare258(next_in - dist, next_in, 258);
|
||||||
|
sub x_tmp2,next_in,x_dist
|
||||||
|
sub x_hash,end_in,next_in
|
||||||
|
compare_max_258_bytes tmp2,next_in,hash,match_length,tmp0,tmp1
|
||||||
|
cmp match_length,3
|
||||||
|
bls get_lit_code
|
||||||
|
|
||||||
|
get_len_code hufftables,match_length,code,code_len,tmp0
|
||||||
|
get_dist_code hufftables,dist,code2,code_len2,tmp0,tmp1,tmp2
|
||||||
|
|
||||||
|
//code |= code2 << code_len;
|
||||||
|
//code_len += code_len2;
|
||||||
|
lsl code2,code2,code_len
|
||||||
|
orr code,code,code2
|
||||||
|
add code_len,code_len,code_len2
|
||||||
|
|
||||||
|
//next_in += match_length;
|
||||||
|
add next_in,next_in,match_length,uxtw
|
||||||
|
|
||||||
|
//write_bits(&state->bitbuf, code, code_len);
|
||||||
|
update_bits stream,code,code_len,m_bits,m_bit_count,m_out_buf
|
||||||
|
|
||||||
|
cmp next_in,loop_end_cnt
|
||||||
|
bls main_loop_start
|
||||||
|
b main_loop_end
|
||||||
|
get_lit_code:
|
||||||
|
//get_lit_code(stream->hufftables, literal & 0xFF, &code, &code_len);
|
||||||
|
and literal,literal,0xff
|
||||||
|
get_lit_code hufftables,literal,code,code_len
|
||||||
|
|
||||||
|
//next_in++;
|
||||||
|
add next_in,next_in,1
|
||||||
|
|
||||||
|
//write_bits(&state->bitbuf, code, code_len);
|
||||||
|
update_bits stream,code,code_len,m_bits,m_bit_count,m_out_buf
|
||||||
|
cmp next_in,loop_end_cnt
|
||||||
|
bls main_loop_start
|
||||||
|
main_loop_end:
|
||||||
|
sub loop_end_cnt,end_in,1
|
||||||
|
cmp next_in,loop_end_cnt
|
||||||
|
bhi update_not_full
|
||||||
|
second_loop_start:
|
||||||
|
cmp m_out_buf,m_out_end
|
||||||
|
bhi update_state_exit
|
||||||
|
ldr literal,[next_in]
|
||||||
|
and literal,literal,0xff
|
||||||
|
get_lit_code hufftables,literal,code,code_len
|
||||||
|
//next_in++;
|
||||||
|
add next_in,next_in,1
|
||||||
|
|
||||||
|
//write_bits(&state->bitbuf, code, code_len);
|
||||||
|
update_bits stream,code,code_len,m_bits,m_bit_count,m_out_buf
|
||||||
|
cmp next_in,loop_end_cnt
|
||||||
|
bls second_loop_start
|
||||||
|
|
||||||
|
update_not_full:
|
||||||
|
cmp m_out_buf,m_out_end
|
||||||
|
bhi update_state_exit
|
||||||
|
|
||||||
|
mov literal,256
|
||||||
|
get_lit_code hufftables,literal,code,code_len
|
||||||
|
|
||||||
|
//write_bits(&state->bitbuf, code, code_len);
|
||||||
|
update_bits stream,code,code_len,m_bits,m_bit_count,m_out_buf
|
||||||
|
ldrh w_end_of_stream, [stream, _end_of_stream]
|
||||||
|
mov w_tmp0,1
|
||||||
|
strb w_tmp0,[stream,_internal_state_has_eob]
|
||||||
|
cmp w_end_of_stream,w_tmp0
|
||||||
|
mov w_tmp0, ZSTATE_TRL
|
||||||
|
mov w_tmp1, ZSTATE_SYNC_FLUSH
|
||||||
|
csel w_tmp0,w_tmp0,w_tmp1,eq
|
||||||
|
str w_tmp0, [stream, _internal_state+_state]
|
||||||
|
|
||||||
|
update_state_exit:
|
||||||
|
update_state stream,start_in,next_in,end_in,m_out_buf,m_out_start,tmp0,tmp1
|
||||||
|
pop_stack
|
||||||
|
ret
|
||||||
|
|
||||||
|
.size isal_deflate_finish_aarch64, .-isal_deflate_finish_aarch64
|
||||||
@ -37,3 +37,24 @@ DEFINE_INTERFACE_DISPATCHER(isal_adler32)
|
|||||||
return PROVIDER_BASIC(adler32);
|
return PROVIDER_BASIC(adler32);
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
DEFINE_INTERFACE_DISPATCHER(isal_deflate_body)
|
||||||
|
{
|
||||||
|
unsigned long auxval = getauxval(AT_HWCAP);
|
||||||
|
|
||||||
|
if (auxval & HWCAP_CRC32)
|
||||||
|
return PROVIDER_INFO(isal_deflate_body_aarch64);
|
||||||
|
|
||||||
|
return PROVIDER_BASIC(isal_deflate_body);
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
DEFINE_INTERFACE_DISPATCHER(isal_deflate_finish)
|
||||||
|
{
|
||||||
|
unsigned long auxval = getauxval(AT_HWCAP);
|
||||||
|
if (auxval & HWCAP_CRC32)
|
||||||
|
return PROVIDER_INFO(isal_deflate_finish_aarch64);
|
||||||
|
|
||||||
|
return PROVIDER_BASIC(isal_deflate_finish);
|
||||||
|
|
||||||
|
}
|
||||||
|
|||||||
@ -29,8 +29,7 @@
|
|||||||
|
|
||||||
#include "aarch64_multibinary.h"
|
#include "aarch64_multibinary.h"
|
||||||
|
|
||||||
mbin_interface_base isal_deflate_body , isal_deflate_body_base
|
|
||||||
mbin_interface_base isal_deflate_finish , isal_deflate_finish_base
|
|
||||||
mbin_interface_base isal_deflate_icf_body_lvl1 , isal_deflate_icf_body_hash_hist_base
|
mbin_interface_base isal_deflate_icf_body_lvl1 , isal_deflate_icf_body_hash_hist_base
|
||||||
mbin_interface_base isal_deflate_icf_body_lvl2 , isal_deflate_icf_body_hash_hist_base
|
mbin_interface_base isal_deflate_icf_body_lvl2 , isal_deflate_icf_body_hash_hist_base
|
||||||
mbin_interface_base isal_deflate_icf_body_lvl3 , icf_body_hash1_fillgreedy_lazy
|
mbin_interface_base isal_deflate_icf_body_lvl3 , icf_body_hash1_fillgreedy_lazy
|
||||||
@ -46,4 +45,6 @@ mbin_interface_base isal_deflate_hash_lvl1 , isal_deflate_hash_base
|
|||||||
mbin_interface_base isal_deflate_hash_lvl2 , isal_deflate_hash_base
|
mbin_interface_base isal_deflate_hash_lvl2 , isal_deflate_hash_base
|
||||||
mbin_interface_base isal_deflate_hash_lvl3 , isal_deflate_hash_base
|
mbin_interface_base isal_deflate_hash_lvl3 , isal_deflate_hash_base
|
||||||
|
|
||||||
|
mbin_interface isal_deflate_body
|
||||||
|
mbin_interface isal_deflate_finish
|
||||||
mbin_interface isal_adler32
|
mbin_interface isal_adler32
|
||||||
|
|||||||
72
igzip/aarch64/lz0a_const_aarch64.h
Normal file
72
igzip/aarch64/lz0a_const_aarch64.h
Normal file
@ -0,0 +1,72 @@
|
|||||||
|
/**********************************************************************
|
||||||
|
Copyright(c) 2019 Arm Corporation All rights reserved.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without
|
||||||
|
modification, are permitted provided that the following conditions
|
||||||
|
are met:
|
||||||
|
* Redistributions of source code must retain the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer.
|
||||||
|
* Redistributions in binary form must reproduce the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer in
|
||||||
|
the documentation and/or other materials provided with the
|
||||||
|
distribution.
|
||||||
|
* Neither the name of Arm Corporation nor the names of its
|
||||||
|
contributors may be used to endorse or promote products derived
|
||||||
|
from this software without specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
**********************************************************************/
|
||||||
|
|
||||||
|
#ifndef __LZ0A_CONST_AARCH64_H__
|
||||||
|
#define __LZ0A_CONST_AARCH64_H__
|
||||||
|
#include "options_aarch64.h"
|
||||||
|
|
||||||
|
#ifdef __ASSEMBLY__
|
||||||
|
.set K , 1024
|
||||||
|
.set D , IGZIP_HIST_SIZE // Amount of history
|
||||||
|
.set LA , 18 * 16 // Max look-ahead, rounded up to 32 byte boundary
|
||||||
|
.set BSIZE , 2*IGZIP_HIST_SIZE + LA // Nominal buffer size
|
||||||
|
|
||||||
|
/// Constants for stateless compression
|
||||||
|
#define LAST_BYTES_COUNT 3 // Bytes to prevent reading out of array bounds
|
||||||
|
#define LA_STATELESS 258 // No round up since no data is copied to a buffer
|
||||||
|
|
||||||
|
.set IGZIP_LVL0_HASH_SIZE , (8 * K)
|
||||||
|
.set IGZIP_HASH8K_HASH_SIZE , (8 * K)
|
||||||
|
.set IGZIP_HASH_HIST_HASH_SIZE , IGZIP_HIST_SIZE
|
||||||
|
.set IGZIP_HASH_MAP_HASH_SIZE , IGZIP_HIST_SIZE
|
||||||
|
|
||||||
|
#define LVL0_HASH_MASK (IGZIP_LVL0_HASH_SIZE - 1)
|
||||||
|
#define HASH8K_HASH_MASK (IGZIP_HASH8K_HASH_SIZE - 1)
|
||||||
|
#define HASH_HIST_HASH_MASK (IGZIP_HASH_HIST_HASH_SIZE - 1)
|
||||||
|
#define HASH_MAP_HASH_MASK (IGZIP_HASH_MAP_HASH_SIZE - 1)
|
||||||
|
|
||||||
|
.set MIN_DEF_MATCH , 3 // Minimum length of a match in deflate
|
||||||
|
.set SHORTEST_MATCH , 4
|
||||||
|
|
||||||
|
.set SLOP , 8
|
||||||
|
|
||||||
|
#define ICF_CODE_BYTES 4
|
||||||
|
#define LIT_LEN_BIT_COUNT 10
|
||||||
|
#define DIST_LIT_BIT_COUNT 9
|
||||||
|
|
||||||
|
#define LIT_LEN_MASK ((1 << LIT_LEN_BIT_COUNT) - 1)
|
||||||
|
#define LIT_DIST_MASK ((1 << DIST_LIT_BIT_COUNT) - 1)
|
||||||
|
|
||||||
|
#define DIST_OFFSET LIT_LEN_BIT_COUNT
|
||||||
|
#define EXTRA_BITS_OFFSET (DIST_OFFSET + DIST_LIT_BIT_COUNT)
|
||||||
|
#define LIT (0x1E << DIST_OFFSET)
|
||||||
|
|
||||||
|
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
71
igzip/aarch64/options_aarch64.h
Normal file
71
igzip/aarch64/options_aarch64.h
Normal file
@ -0,0 +1,71 @@
|
|||||||
|
/**********************************************************************
|
||||||
|
Copyright(c) 2019 Arm Corporation All rights reserved.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without
|
||||||
|
modification, are permitted provided that the following conditions
|
||||||
|
are met:
|
||||||
|
* Redistributions of source code must retain the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer.
|
||||||
|
* Redistributions in binary form must reproduce the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer in
|
||||||
|
the documentation and/or other materials provided with the
|
||||||
|
distribution.
|
||||||
|
* Neither the name of Arm Corporation nor the names of its
|
||||||
|
contributors may be used to endorse or promote products derived
|
||||||
|
from this software without specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
**********************************************************************/
|
||||||
|
|
||||||
|
#ifndef __OPTIONS_AARCH64_H__
|
||||||
|
#define __OPTIONS_AARCH64_H__
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __ASSEMBLY__
|
||||||
|
|
||||||
|
/// Options:dir
|
||||||
|
/// m - reschedule mem reads
|
||||||
|
/// e b - bitbuff style
|
||||||
|
/// t s x - compare style
|
||||||
|
/// h - limit hash updates
|
||||||
|
/// l - use longer huffman table
|
||||||
|
/// f - fix cache read
|
||||||
|
|
||||||
|
#ifndef IGZIP_HIST_SIZE
|
||||||
|
#define IGZIP_HIST_SIZE (32 * 1024)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (IGZIP_HIST_SIZE > (32 * 1024))
|
||||||
|
#undef IGZIP_HIST_SIZE
|
||||||
|
#define IGZIP_HIST_SIZE (32 * 1024)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef LONGER_HUFFTABLE
|
||||||
|
#if (IGZIP_HIST_SIZE > 8 * 1024)
|
||||||
|
#undef IGZIP_HIST_SIZE
|
||||||
|
#define IGZIP_HIST_SIZE (8 * 1024)
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/// (h) limit hash update
|
||||||
|
#define LIMIT_HASH_UPDATE
|
||||||
|
|
||||||
|
/// (f) fix cache read problem
|
||||||
|
#define FIX_CACHE_READ
|
||||||
|
|
||||||
|
#define ISAL_DEF_MAX_HDR_SIZE 328
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
57
igzip/aarch64/stdmac_aarch64.h
Normal file
57
igzip/aarch64/stdmac_aarch64.h
Normal file
@ -0,0 +1,57 @@
|
|||||||
|
/**********************************************************************
|
||||||
|
Copyright(c) 2019 Arm Corporation All rights reserved.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without
|
||||||
|
modification, are permitted provided that the following conditions
|
||||||
|
are met:
|
||||||
|
* Redistributions of source code must retain the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer.
|
||||||
|
* Redistributions in binary form must reproduce the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer in
|
||||||
|
the documentation and/or other materials provided with the
|
||||||
|
distribution.
|
||||||
|
* Neither the name of Arm Corporation nor the names of its
|
||||||
|
contributors may be used to endorse or promote products derived
|
||||||
|
from this software without specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
**********************************************************************/
|
||||||
|
|
||||||
|
#ifndef __STDMAC_AARCH64_H__
|
||||||
|
#define __STDMAC_AARCH64_H__
|
||||||
|
|
||||||
|
#ifdef __ASSEMBLY__
|
||||||
|
|
||||||
|
#define DEBUG_STACK 144
|
||||||
|
|
||||||
|
.macro push_stack
|
||||||
|
stp x29, x30,[sp,0-DEBUG_STACK]!
|
||||||
|
mov x29, sp
|
||||||
|
stp x19, x20, [sp, 16]
|
||||||
|
stp x21, x22, [sp, 32]
|
||||||
|
stp x23, x24, [sp, 48]
|
||||||
|
stp x25, x26, [sp, 64]
|
||||||
|
stp x27, x28, [sp, 80]
|
||||||
|
.endm
|
||||||
|
.macro pop_stack
|
||||||
|
ldp x19, x20, [sp, 16]
|
||||||
|
ldp x21, x22, [sp, 32]
|
||||||
|
ldp x23, x24, [sp, 48]
|
||||||
|
ldp x25, x26, [sp, 64]
|
||||||
|
ldp x27, x28, [sp, 80]
|
||||||
|
|
||||||
|
ldp x29, x30, [sp], DEBUG_STACK
|
||||||
|
.endm
|
||||||
|
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
Loading…
Reference in New Issue
Block a user