generic-library/isa-l
1
0
Fork 0
mirror of https://github.com/intel/isa-l.git synced 2025-10-28 11:31:51 +01:00
Code Issues Projects Releases Wiki Activity

erasure_code: optimize RVV implementation

Browse Source 
The ISA-L EC code has been written using RVV vector instructions and the minimum multiplication table,
resulting in a performance improvement of over 10 times compared to the existing implementation.

Signed-off-by: Shuo Lv <lv.shuo@sanechips.com.cn>
This commit is contained in:
lvshuo
2025-06-03 15:54:11 +08:00
committed by Pablo de Lara
parent f2883f24fd
commit d414b2702a
27 changed files with 3137 additions and 536 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
erasure_code/erasure_code_test.c
View File

@@ -50,6 +50,9 @@
#define EFENCE_TEST_MIN_SIZE 16
#define EFENCE_TEST_MAX_SIZE EFENCE_TEST_MIN_SIZE + 0x100
#if HAVE_RVV
#define EC_ALIGNED_ADDR
#endif
#ifdef EC_ALIGNED_ADDR
// Define power of 2 range to check ptr, len alignment
#define PTR_ALIGN_CHK_B 0