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build: Avoid requiring AVX512 define when using dispatch functions
Change-Id: I76af2d6ab7eb61ae531bbc7427650d08737c20ab Signed-off-by: Roy Oursler <roy.j.oursler@intel.com>
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@ -81,18 +81,10 @@ mbin_interface gf_vect_mad
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%else
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mbin_dispatch_init5 gf_vect_mul, gf_vect_mul_base, gf_vect_mul_sse, gf_vect_mul_avx, gf_vect_mul_avx
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%ifdef HAVE_AS_KNOWS_AVX512
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mbin_dispatch_init6 ec_encode_data, ec_encode_data_base, ec_encode_data_sse, ec_encode_data_avx, ec_encode_data_avx2, ec_encode_data_avx512
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mbin_dispatch_init6 ec_encode_data_update, ec_encode_data_update_base, ec_encode_data_update_sse, ec_encode_data_update_avx, ec_encode_data_update_avx2, ec_encode_data_update_avx512
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mbin_dispatch_init6 gf_vect_mad, gf_vect_mad_base, gf_vect_mad_sse, gf_vect_mad_avx, gf_vect_mad_avx2, gf_vect_mad_avx512
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mbin_dispatch_init6 gf_vect_dot_prod, gf_vect_dot_prod_base, gf_vect_dot_prod_sse, gf_vect_dot_prod_avx, gf_vect_dot_prod_avx2, gf_vect_dot_prod_avx512
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%else
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mbin_dispatch_init5 ec_encode_data, ec_encode_data_base, ec_encode_data_sse, ec_encode_data_avx, ec_encode_data_avx2
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mbin_dispatch_init5 ec_encode_data_update, ec_encode_data_update_base, ec_encode_data_update_sse, ec_encode_data_update_avx, ec_encode_data_update_avx2
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mbin_dispatch_init5 gf_vect_mad, gf_vect_mad_base, gf_vect_mad_sse, gf_vect_mad_avx, gf_vect_mad_avx2
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mbin_dispatch_init5 gf_vect_dot_prod, gf_vect_dot_prod_base, gf_vect_dot_prod_sse, gf_vect_dot_prod_avx, gf_vect_dot_prod_avx2
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%endif
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%endif
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;;; func core, ver, snum
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@ -109,7 +109,6 @@ mbin_dispatch_init5 isal_deflate_icf_finish_lvl3, isal_deflate_icf_finish_hash_m
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mbin_interface isal_update_histogram
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mbin_dispatch_init5 isal_update_histogram, isal_update_histogram_base, isal_update_histogram_01, isal_update_histogram_01, isal_update_histogram_04
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%ifdef HAVE_AS_KNOWS_AVX512
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mbin_interface encode_deflate_icf
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mbin_dispatch_init6 encode_deflate_icf, encode_deflate_icf_base, encode_deflate_icf_base, encode_deflate_icf_base, encode_deflate_icf_04, encode_deflate_icf_06
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@ -118,16 +117,6 @@ mbin_dispatch_init6 set_long_icf_fg, set_long_icf_fg_base, set_long_icf_fg_base,
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mbin_interface gen_icf_map_lh1
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mbin_dispatch_init6 gen_icf_map_lh1, gen_icf_map_h1_base, gen_icf_map_h1_base, gen_icf_map_h1_base, gen_icf_map_lh1_04, gen_icf_map_lh1_06
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%else
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mbin_interface encode_deflate_icf
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mbin_dispatch_init5 encode_deflate_icf, encode_deflate_icf_base, encode_deflate_icf_base, encode_deflate_icf_base, encode_deflate_icf_04
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mbin_interface set_long_icf_fg
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mbin_dispatch_init5 set_long_icf_fg, set_long_icf_fg_base, set_long_icf_fg_base, set_long_icf_fg_base, set_long_icf_fg_04
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mbin_interface gen_icf_map_lh1
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mbin_dispatch_init5 gen_icf_map_lh1, gen_icf_map_h1_base, gen_icf_map_h1_base, gen_icf_map_h1_base, gen_icf_map_lh1_04
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%endif
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mbin_interface isal_adler32
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mbin_dispatch_init5 isal_adler32, adler32_base, adler32_sse, adler32_sse, adler32_avx2_4
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@ -143,4 +132,3 @@ mbin_dispatch_init5 isal_deflate_hash_lvl2, isal_deflate_hash_base, isal_deflate
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mbin_interface isal_deflate_hash_lvl3
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mbin_dispatch_init5 isal_deflate_hash_lvl3, isal_deflate_hash_base, isal_deflate_hash_base, isal_deflate_hash_base, isal_deflate_hash_mad_base
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@ -235,6 +235,7 @@
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ret
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%endmacro
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%ifdef HAVE_AS_KNOWS_AVX512
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;;;;;
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; mbin_dispatch_init6 parameters
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; 1-> function name
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@ -304,4 +305,10 @@
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ret
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%endmacro
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%else
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%macro mbin_dispatch_init6 6
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mbin_dispatch_init5 %1, %2, %3, %4, %5
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%endmacro
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%endif
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%endif ; ifndef _MULTIBINARY_ASM_
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@ -56,13 +56,9 @@ extern xor_check_sse
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mbin_interface xor_gen
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mbin_interface pq_gen
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%ifdef HAVE_AS_KNOWS_AVX512
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mbin_dispatch_init6 xor_gen, xor_gen_base, xor_gen_sse, xor_gen_avx, xor_gen_avx, xor_gen_avx512
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mbin_dispatch_init6 pq_gen, pq_gen_base, pq_gen_sse, pq_gen_avx, pq_gen_avx2, pq_gen_avx512
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%else
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mbin_dispatch_init5 xor_gen, xor_gen_base, xor_gen_sse, xor_gen_avx, xor_gen_avx
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mbin_dispatch_init5 pq_gen, pq_gen_base, pq_gen_sse, pq_gen_avx, pq_gen_avx2
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%endif
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section .data
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