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igzip: implement encode_deflate_icf with assembly
Change-Id: I90b12da2d2a96bfdb47d29ab329648247a756585 Signed-off-by: Zhiyuan Zhu <zhiyuan.zhu@arm.com>
This commit is contained in:
Zhiyuan Zhu
Greg Tucker
parent
5eeb33f69c
commit
683364c47b
@ -48,6 +48,7 @@ lsrc_aarch64 += igzip/aarch64/igzip_inflate_multibinary_arm64.S \
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igzip/aarch64/isal_deflate_icf_body_hash_hist.S \
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igzip/aarch64/isal_deflate_icf_finish_hash_hist.S \
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igzip/aarch64/igzip_set_long_icf_fg.S \
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igzip/aarch64/encode_df.S \
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igzip/aarch64/isal_update_histogram.S \
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igzip/aarch64/igzip_deflate_hash_aarch64.S \
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igzip/proc_heap_base.c
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159
igzip/aarch64/encode_df.S
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159
igzip/aarch64/encode_df.S
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@ -0,0 +1,159 @@
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/**********************************************************************
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Copyright(c) 2019 Arm Corporation All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of Arm Corporation nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**********************************************************************/
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.arch armv8-a+crc
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.text
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.align 2
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#include "lz0a_const_aarch64.h"
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#include "data_struct_aarch64.h"
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#include "huffman_aarch64.h"
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#include "bitbuf2_aarch64.h"
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#include "stdmac_aarch64.h"
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/*
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declare Macros
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*/
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.macro declare_generic_reg name:req,reg:req,default:req
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\name .req \default\reg
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w_\name .req w\reg
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x_\name .req x\reg
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.endm
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.global encode_deflate_icf_aarch64
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.type encode_deflate_icf_aarch64, %function
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/*
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struct deflate_icf *encode_deflate_icf_base(struct deflate_icf *next_in,
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struct deflate_icf *end_in, struct BitBuf2 *bb,
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struct hufftables_icf *hufftables)
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*/
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// parameters
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declare_generic_reg next_in, 0,x
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declare_generic_reg end_in, 1,x
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declare_generic_reg bb, 2,x
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declare_generic_reg hufftables, 3,x
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// local variable
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declare_generic_reg bb_out_end, 4,x
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declare_generic_reg bb_bit_count, 5,w
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declare_generic_reg dist_extra, 6,x
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declare_generic_reg dist_lit_table, 7,x
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declare_generic_reg code_and_extra, 8,x
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declare_generic_reg bb_out_buf, 9,x
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declare_generic_reg bb_bits, 10,x
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declare_generic_reg d_length, 11,x
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declare_generic_reg l_length, 12,x
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declare_generic_reg d_extra_bit_count, 13,x
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declare_generic_reg code_sum, 4,x
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declare_generic_reg count_sum, 7,x
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declare_generic_reg tmp0, 14,x
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declare_generic_reg tmp1, 15,x
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// bit buffer offset
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.equ offset_m_bits, 0
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.equ offset_m_bit_count, 8
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.equ offset_m_out_buf, 16
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.equ offset_m_out_end, 24
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encode_deflate_icf_aarch64:
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cmp next_in, end_in
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bcs .done
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ldp bb_out_buf, bb_out_end, [bb, offset_m_out_buf]
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cmp bb_out_end, bb_out_buf
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bcc .done
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ldr bb_bit_count, [bb, offset_m_bit_count]
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ldr bb_bits, [bb, offset_m_bits]
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b .loop_start
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.align 3
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.loop:
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ldr bb_out_end, [bb, offset_m_out_end]
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cmp bb_out_end, bb_out_buf
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bcc .done
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.loop_start:
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ldrh w_code_and_extra, [next_in]
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add next_in, next_in, 4
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ldr w_dist_lit_table, [next_in, -4]
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and code_and_extra, code_and_extra, 1023
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ldrh w_dist_extra, [next_in, -2]
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add code_and_extra, code_and_extra, 31
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ubfx x_dist_lit_table, x_dist_lit_table, 10, 9
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add x_tmp0, hufftables, code_and_extra, lsl 2
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ubfx x_dist_extra, x_dist_extra, 3, 13
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lsl x_dist_lit_table, x_dist_lit_table, 2
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ldr w_code_and_extra, [hufftables, code_and_extra, lsl 2]
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add x_d_extra_bit_count, hufftables, x_dist_lit_table
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ldrb w_l_length, [x_tmp0, 3]
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and code_and_extra, code_and_extra, 0xffffff
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ldrh w_code_sum, [hufftables, x_dist_lit_table]
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ldrb w_d_length, [x_d_extra_bit_count, 3]
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add w_l_length, w_l_length, bb_bit_count
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ldrb w_d_extra_bit_count, [x_d_extra_bit_count, 2]
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lsl x_tmp0, code_and_extra, x_bb_bit_count
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add bb_bit_count, w_d_length, w_l_length
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lsl x_code_sum, x_code_sum, x_l_length
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orr x_code_sum, x_code_sum, x_tmp0
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add w_count_sum, w_d_extra_bit_count, bb_bit_count
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lsl x_bb_bit_count, x_dist_extra, x_bb_bit_count
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orr x_bb_bit_count, x_bb_bit_count, bb_bits
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orr x_tmp0, x_code_sum, x_bb_bit_count // me->m_bits => x_tmp0
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str x_tmp0, [bb, offset_m_bits] // me->m_bits => x_tmp0
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str w_count_sum, [bb, offset_m_bit_count]
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str x_tmp0, [bb_out_buf] // me->m_bits => x_tmp0
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ldr bb_bit_count, [bb, offset_m_bit_count]
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ldr bb_bits, [bb, offset_m_bits]
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and w_tmp0, bb_bit_count, -8 // bits => w_tmp0
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ldr bb_out_buf, [bb, offset_m_out_buf]
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lsr w_tmp1, bb_bit_count, 3 // bits/8 => w_tmp1
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lsr bb_bits, bb_bits, x_tmp0 // bits => x_tmp0
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sub bb_bit_count, bb_bit_count, w_tmp0 // bits => w_tmp0
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add bb_out_buf, bb_out_buf, x_tmp1 // bits/8 => x_tmp1
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str bb_bits, [bb,offset_m_bits]
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str bb_bit_count, [bb, offset_m_bit_count]
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str bb_out_buf, [bb, offset_m_out_buf]
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cmp end_in, next_in
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bhi .loop
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.done:
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ret
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.size encode_deflate_icf_aarch64, .-encode_deflate_icf_aarch64
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@ -118,6 +118,11 @@ DEFINE_INTERFACE_DISPATCHER(set_long_icf_fg)
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return PROVIDER_INFO(set_long_icf_fg_aarch64);
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}
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DEFINE_INTERFACE_DISPATCHER(encode_deflate_icf)
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{
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return PROVIDER_INFO(encode_deflate_icf_aarch64);
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}
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DEFINE_INTERFACE_DISPATCHER(isal_update_histogram)
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{
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unsigned long auxval = getauxval(AT_HWCAP);
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@ -37,7 +37,7 @@ mbin_interface isal_deflate_icf_finish_lvl1
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mbin_interface isal_deflate_icf_finish_lvl2
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mbin_interface isal_deflate_icf_finish_lvl3
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mbin_interface isal_update_histogram
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mbin_interface_base encode_deflate_icf , encode_deflate_icf_base
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mbin_interface encode_deflate_icf
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mbin_interface set_long_icf_fg
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mbin_interface_base gen_icf_map_lh1 , gen_icf_map_h1_base
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mbin_interface isal_deflate_hash_lvl0
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