From 65e89717dfd1835fc401f0bd4101d710a731a75e Mon Sep 17 00:00:00 2001 From: Pablo de Lara Date: Tue, 14 Nov 2023 14:43:16 +0000 Subject: [PATCH] erasure_code: implement EC update with AVX512 + GFNI Signed-off-by: Pablo de Lara --- Makefile.nmake | 6 + erasure_code/Makefile.am | 8 +- erasure_code/ec_highlevel_func.c | 45 ++++ erasure_code/ec_multibinary.asm | 3 +- erasure_code/gf_2vect_mad_avx512_gfni.asm | 187 ++++++++++++++++ erasure_code/gf_3vect_mad_avx512.asm | 2 +- erasure_code/gf_3vect_mad_avx512_gfni.asm | 202 +++++++++++++++++ erasure_code/gf_4vect_mad_avx512_gfni.asm | 221 +++++++++++++++++++ erasure_code/gf_5vect_mad_avx512_gfni.asm | 238 ++++++++++++++++++++ erasure_code/gf_6vect_mad_avx512_gfni.asm | 257 ++++++++++++++++++++++ erasure_code/gf_vect_mad_avx512_gfni.asm | 173 +++++++++++++++ 11 files changed, 1339 insertions(+), 3 deletions(-) create mode 100644 erasure_code/gf_2vect_mad_avx512_gfni.asm create mode 100644 erasure_code/gf_3vect_mad_avx512_gfni.asm create mode 100644 erasure_code/gf_4vect_mad_avx512_gfni.asm create mode 100644 erasure_code/gf_5vect_mad_avx512_gfni.asm create mode 100644 erasure_code/gf_6vect_mad_avx512_gfni.asm create mode 100644 erasure_code/gf_vect_mad_avx512_gfni.asm diff --git a/Makefile.nmake b/Makefile.nmake index d35be22..804d59c 100644 --- a/Makefile.nmake +++ b/Makefile.nmake @@ -103,6 +103,12 @@ objs = \ bin\gf_4vect_mad_avx512.obj \ bin\gf_5vect_mad_avx512.obj \ bin\gf_6vect_mad_avx512.obj \ + bin\gf_vect_mad_avx512_gfni.obj \ + bin\gf_2vect_mad_avx512_gfni.obj \ + bin\gf_3vect_mad_avx512_gfni.obj \ + bin\gf_4vect_mad_avx512_gfni.obj \ + bin\gf_5vect_mad_avx512_gfni.obj \ + bin\gf_6vect_mad_avx512_gfni.obj \ bin\xor_gen_sse.obj \ bin\pq_gen_sse.obj \ bin\xor_check_sse.obj \ diff --git a/erasure_code/Makefile.am b/erasure_code/Makefile.am index 1bdbeea..b4fedb3 100644 --- a/erasure_code/Makefile.am +++ b/erasure_code/Makefile.am @@ -95,7 +95,13 @@ lsrc_x86_64 += \ erasure_code/gf_3vect_mad_avx512.asm \ erasure_code/gf_4vect_mad_avx512.asm \ erasure_code/gf_5vect_mad_avx512.asm \ - erasure_code/gf_6vect_mad_avx512.asm + erasure_code/gf_6vect_mad_avx512.asm \ + erasure_code/gf_vect_mad_avx512_gfni.asm \ + erasure_code/gf_2vect_mad_avx512_gfni.asm \ + erasure_code/gf_3vect_mad_avx512_gfni.asm \ + erasure_code/gf_4vect_mad_avx512_gfni.asm \ + erasure_code/gf_5vect_mad_avx512_gfni.asm \ + erasure_code/gf_6vect_mad_avx512_gfni.asm lsrc_x86_32 += \ erasure_code/ec_highlevel_func.c \ diff --git a/erasure_code/ec_highlevel_func.c b/erasure_code/ec_highlevel_func.c index 34b70a5..4c1bb7a 100644 --- a/erasure_code/ec_highlevel_func.c +++ b/erasure_code/ec_highlevel_func.c @@ -254,6 +254,19 @@ extern void gf_5vect_dot_prod_avx512_gfni(int len, int k, unsigned char *g_tbls, extern void gf_6vect_dot_prod_avx512_gfni(int len, int k, unsigned char *g_tbls, unsigned char **data, unsigned char **coding); +extern void gf_vect_mad_avx512_gfni(int len, int vec, int vec_i, unsigned char *gftbls, + unsigned char *src, unsigned char *dest); +extern void gf_2vect_mad_avx512_gfni(int len, int vec, int vec_i, unsigned char *gftbls, + unsigned char *src, unsigned char **dest); +extern void gf_3vect_mad_avx512_gfni(int len, int vec, int vec_i, unsigned char *gftbls, + unsigned char *src, unsigned char **dest); +extern void gf_4vect_mad_avx512_gfni(int len, int vec, int vec_i, unsigned char *gftbls, + unsigned char *src, unsigned char **dest); +extern void gf_5vect_mad_avx512_gfni(int len, int vec, int vec_i, unsigned char *gftbls, + unsigned char *src, unsigned char **dest); +extern void gf_6vect_mad_avx512_gfni(int len, int vec, int vec_i, unsigned char *gftbls, + unsigned char *src, unsigned char **dest); + void ec_init_tables_gfni(int k, int rows, unsigned char *a, unsigned char *g_tbls) { int i, j; @@ -298,6 +311,38 @@ void ec_encode_data_avx512_gfni(int len, int k, int rows, unsigned char *g_tbls, } } +void ec_encode_data_update_avx512_gfni(int len, int k, int rows, int vec_i, + unsigned char *g_tbls, unsigned char *data, + unsigned char **coding) +{ + while (rows >= 6) { + gf_6vect_mad_avx512_gfni(len, k, vec_i, g_tbls, data, coding); + g_tbls += 6 * k * 8; + coding += 6; + rows -= 6; + } + switch (rows) { + case 5: + gf_5vect_mad_avx512_gfni(len, k, vec_i, g_tbls, data, coding); + break; + case 4: + gf_4vect_mad_avx512_gfni(len, k, vec_i, g_tbls, data, coding); + break; + case 3: + gf_3vect_mad_avx512_gfni(len, k, vec_i, g_tbls, data, coding); + break; + case 2: + gf_2vect_mad_avx512_gfni(len, k, vec_i, g_tbls, data, coding); + break; + case 1: + gf_vect_mad_avx512_gfni(len, k, vec_i, g_tbls, data, *coding); + break; + case 0: + default: + break; + } +} + #endif // AS_FEATURE_LEVEL >= 10 #endif // HAVE_AS_KNOWS_AVX512 diff --git a/erasure_code/ec_multibinary.asm b/erasure_code/ec_multibinary.asm index c41d61a..a80d88c 100644 --- a/erasure_code/ec_multibinary.asm +++ b/erasure_code/ec_multibinary.asm @@ -56,6 +56,7 @@ %if (AS_FEATURE_LEVEL) >= 10 extern ec_init_tables_gfni extern ec_encode_data_avx512_gfni + extern ec_encode_data_update_avx512_gfni %endif extern ec_init_tables_base @@ -91,7 +92,7 @@ mbin_interface ec_init_tables mbin_dispatch_init5 gf_vect_mul, gf_vect_mul_base, gf_vect_mul_sse, gf_vect_mul_avx, gf_vect_mul_avx mbin_dispatch_init7 ec_encode_data, ec_encode_data_base, ec_encode_data_sse, ec_encode_data_avx, ec_encode_data_avx2, ec_encode_data_avx512, ec_encode_data_avx512_gfni - mbin_dispatch_init6 ec_encode_data_update, ec_encode_data_update_base, ec_encode_data_update_sse, ec_encode_data_update_avx, ec_encode_data_update_avx2, ec_encode_data_update_avx512 + mbin_dispatch_init7 ec_encode_data_update, ec_encode_data_update_base, ec_encode_data_update_sse, ec_encode_data_update_avx, ec_encode_data_update_avx2, ec_encode_data_update_avx512, ec_encode_data_update_avx512_gfni mbin_dispatch_init6 gf_vect_mad, gf_vect_mad_base, gf_vect_mad_sse, gf_vect_mad_avx, gf_vect_mad_avx2, gf_vect_mad_avx512 mbin_dispatch_init6 gf_vect_dot_prod, gf_vect_dot_prod_base, gf_vect_dot_prod_sse, gf_vect_dot_prod_avx, gf_vect_dot_prod_avx2, gf_vect_dot_prod_avx512 mbin_dispatch_init7 ec_init_tables, ec_init_tables_base, ec_init_tables_base, ec_init_tables_base, ec_init_tables_base, ec_init_tables_base, ec_init_tables_gfni diff --git a/erasure_code/gf_2vect_mad_avx512_gfni.asm b/erasure_code/gf_2vect_mad_avx512_gfni.asm new file mode 100644 index 0000000..a656f4e --- /dev/null +++ b/erasure_code/gf_2vect_mad_avx512_gfni.asm @@ -0,0 +1,187 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright(c) 2023 Intel Corporation All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in +; the documentation and/or other materials provided with the +; distribution. +; * Neither the name of Intel Corporation nor the names of its +; contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +;;; +;;; gf_2vect_mad_avx512_gfni(len, vec, vec_i, mul_array, src, dest); +;;; + +%include "reg_sizes.asm" +%include "gf_vect_gfni.inc" + +%if AS_FEATURE_LEVEL >= 10 + +%ifidn __OUTPUT_FORMAT__, elf64 + %define arg0 rdi + %define arg1 rsi + %define arg2 rdx + %define arg3 rcx + %define arg4 r8 + %define arg5 r9 + %define tmp r11 + %define tmp2 r10 + %define func(x) x: endbranch + %define FUNC_SAVE + %define FUNC_RESTORE +%endif + +%ifidn __OUTPUT_FORMAT__, win64 + %define arg0 rcx + %define arg1 rdx + %define arg2 r8 + %define arg3 r9 + %define arg4 r12 + %define arg5 r13 + %define tmp r11 + %define tmp2 r10 + %define stack_size 16 + 3*8 ; must be an odd multiple of 8 + %define arg(x) [rsp + stack_size + 8 + 8*x] + + %define func(x) proc_frame x + %macro FUNC_SAVE 0 + sub rsp, stack_size + vmovdqa [rsp + 16*0], xmm6 + mov [rsp + 16 + 0*8], r12 + mov [rsp + 16 + 1*8], r13 + end_prolog + mov arg4, arg(4) + mov arg5, arg(5) + %endmacro + + %macro FUNC_RESTORE 0 + vmovdqa xmm6, [rsp + 16*0] + mov r12, [rsp + 16 + 0*8] + mov r13, [rsp + 16 + 1*8] + add rsp, stack_size + %endmacro +%endif + +%define len arg0 +%define vec arg1 +%define vec_i arg2 +%define mul_array arg3 +%define src arg4 +%define dest1 arg5 +%define pos rax +%define dest2 tmp2 + +%ifndef EC_ALIGNED_ADDR +;;; Use Un-aligned load/store + %define XLDR vmovdqu8 + %define XSTR vmovdqu8 +%else +;;; Use Non-temporal load/stor + %ifdef NO_NT_LDST + %define XLDR vmovdqa64 + %define XSTR vmovdqa64 + %else + %define XLDR vmovntdqa + %define XSTR vmovntdq + %endif +%endif + +default rel +[bits 64] +section .text + +%define x0 zmm0 +%define xd1 zmm1 +%define xd2 zmm2 +%define xgft1 zmm3 +%define xgft2 zmm4 +%define xret1 zmm5 +%define xret2 zmm6 + +;; +;; Encodes 64 bytes of a single source into 2x 64 bytes (parity disks) +;; +%macro ENCODE_64B_2 0-1 +%define %%KMASK %1 + +%if %0 == 1 + vmovdqu8 x0{%%KMASK}, [src + pos] ;Get next source vector + vmovdqu8 xd1{%%KMASK}, [dest1 + pos] ;Get next dest vector + vmovdqu8 xd2{%%KMASK}, [dest2 + pos] ;Get next dest vector +%else + XLDR x0, [src + pos] ;Get next source vector + XLDR xd1, [dest1 + pos] ;Get next dest vector + XLDR xd2, [dest2 + pos] ;Get next dest vector +%endif + + GF_MUL_XOR x0, xgft1, xret1, xd1, xgft2, xret2, xd2 + +%if %0 == 1 + vmovdqu8 [dest1 + pos]{%%KMASK}, xd1 + vmovdqu8 [dest2 + pos]{%%KMASK}, xd2 +%else + XSTR [dest1 + pos], xd1 + XSTR [dest2 + pos], xd2 +%endif +%endmacro + +align 16 +mk_global gf_2vect_mad_avx512_gfni, function +func(gf_2vect_mad_avx512_gfni) + FUNC_SAVE + + xor pos, pos + shl vec_i, 3 ;Multiply by 8 + shl vec, 3 + lea tmp, [mul_array + vec_i] + vbroadcastf32x2 xgft1, [tmp] + vbroadcastf32x2 xgft2, [tmp + vec] + mov dest2, [dest1 + 8] ; reuse mul_array + mov dest1, [dest1] + +.loop64: + ENCODE_64B_2 + + add pos, 64 ;Loop on 64 bytes at a time + sub len, 64 + cmp len, 64 + jge .loop64 + +.len_lt_64: + cmp len, 0 + jle .exit + + xor tmp, tmp + bts tmp, len + dec tmp + kmovq k1, tmp + + ENCODE_64B_2 k1 + +.exit: + vzeroupper + + FUNC_RESTORE + ret + +endproc_frame +%endif ; if AS_FEATURE_LEVEL >= 10 diff --git a/erasure_code/gf_3vect_mad_avx512.asm b/erasure_code/gf_3vect_mad_avx512.asm index 3538863..9d77c01 100644 --- a/erasure_code/gf_3vect_mad_avx512.asm +++ b/erasure_code/gf_3vect_mad_avx512.asm @@ -204,7 +204,7 @@ func(gf_3vect_mad_avx512) vpshufb xtmph3 {k1}{z}, xgft3_hi, x0 ;Lookup mul table of high nibble vpshufb xtmpl3 {k1}{z}, xgft3_lo, xtmpa ;Lookup mul table of low nibble vpxorq xtmph3, xtmph3, xtmpl3 ;GF add high and low partials - vpxorq xd3, xd3, xtmph3 ;xd2 += partial + vpxorq xd3, xd3, xtmph3 ;xd3 += partial XSTR [dest1+pos], xd1 XSTR [dest2+pos], xd2 diff --git a/erasure_code/gf_3vect_mad_avx512_gfni.asm b/erasure_code/gf_3vect_mad_avx512_gfni.asm new file mode 100644 index 0000000..b609ed6 --- /dev/null +++ b/erasure_code/gf_3vect_mad_avx512_gfni.asm @@ -0,0 +1,202 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright(c) 2023 Intel Corporation All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in +; the documentation and/or other materials provided with the +; distribution. +; * Neither the name of Intel Corporation nor the names of its +; contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +;;; +;;; gf_3vect_mad_avx512_gfni(len, vec, vec_i, mul_array, src, dest); +;;; + +%include "reg_sizes.asm" +%include "gf_vect_gfni.inc" + +%if AS_FEATURE_LEVEL >= 10 + +%ifidn __OUTPUT_FORMAT__, elf64 + %define arg0 rdi + %define arg1 rsi + %define arg2 rdx + %define arg3 rcx + %define arg4 r8 + %define arg5 r9 + %define tmp r11 + %define func(x) x: endbranch + %define FUNC_SAVE + %define FUNC_RESTORE +%endif + +%ifidn __OUTPUT_FORMAT__, win64 + %define arg0 rcx + %define arg1 rdx + %define arg2 r8 + %define arg3 r9 + %define arg4 r12 ; must be saved, loaded and restored + %define arg5 r13 ; must be saved and restored + %define tmp r11 + %define stack_size 16*4 + 3*8 + %define arg(x) [rsp + stack_size + 8 + 8*x] + %define func(x) proc_frame x + + %macro FUNC_SAVE 0 + sub rsp, stack_size + vmovdqa [rsp + 16*0], xmm6 + vmovdqa [rsp + 16*1], xmm7 + vmovdqa [rsp + 16*2], xmm8 + vmovdqa [rsp + 16*3], xmm9 + mov [rsp + 4*16 + 0*8], r12 + mov [rsp + 4*16 + 1*8], r13 + end_prolog + mov arg4, arg(4) + mov arg5, arg(5) + %endmacro + + %macro FUNC_RESTORE 0 + vmovdqa xmm6, [rsp + 16*0] + vmovdqa xmm7, [rsp + 16*1] + vmovdqa xmm8, [rsp + 16*2] + vmovdqa xmm9, [rsp + 16*3] + mov r12, [rsp + 4*16 + 0*8] + mov r13, [rsp + 4*16 + 1*8] + add rsp, stack_size + %endmacro +%endif + +%define len arg0 +%define vec arg1 +%define vec_i arg2 +%define mul_array arg3 +%define src arg4 +%define dest1 arg5 +%define pos rax +%define dest2 mul_array +%define dest3 vec_i + +%ifndef EC_ALIGNED_ADDR +;;; Use Un-aligned load/store + %define XLDR vmovdqu8 + %define XSTR vmovdqu8 +%else +;;; Use Non-temporal load/stor + %ifdef NO_NT_LDST + %define XLDR vmovdqa64 + %define XSTR vmovdqa64 + %else + %define XLDR vmovntdqa + %define XSTR vmovntdq + %endif +%endif + +default rel +[bits 64] +section .text + +%define x0 zmm0 +%define xgft1 zmm1 +%define xgft2 zmm2 +%define xgft3 zmm3 +%define xd1 zmm4 +%define xd2 zmm5 +%define xd3 zmm6 + +%define xret1 zmm7 +%define xret2 zmm8 +%define xret3 zmm9 + +;; +;; Encodes 64 bytes of a single source into 3x 64 bytes (parity disks) +;; +%macro ENCODE_64B_3 0-1 +%define %%KMASK %1 + +%if %0 == 1 + vmovdqu8 x0{%%KMASK}, [src + pos] ;Get next source vector + vmovdqu8 xd1{%%KMASK}, [dest1 + pos] ;Get next dest vector + vmovdqu8 xd2{%%KMASK}, [dest2 + pos] ;Get next dest vector + vmovdqu8 xd3{%%KMASK}, [dest3 + pos] ;Get next dest vector +%else + XLDR x0, [src + pos] ;Get next source vector + XLDR xd1, [dest1 + pos] ;Get next dest vector + XLDR xd2, [dest2 + pos] ;Get next dest vector + XLDR xd3, [dest3 + pos] ;Get next dest vector +%endif + + GF_MUL_XOR x0, xgft1, xret1, xd1, xgft2, xret2, xd2, xgft3, xret3, xd3 + +%if %0 == 1 + vmovdqu8 [dest1 + pos]{%%KMASK}, xd1 + vmovdqu8 [dest2 + pos]{%%KMASK}, xd2 + vmovdqu8 [dest3 + pos]{%%KMASK}, xd3 +%else + XSTR [dest1 + pos], xd1 + XSTR [dest2 + pos], xd2 + XSTR [dest3 + pos], xd3 +%endif +%endmacro + +align 16 +mk_global gf_3vect_mad_avx512_gfni, function +func(gf_3vect_mad_avx512_gfni) + FUNC_SAVE + + xor pos, pos + shl vec_i, 3 ;Multiply by 8 + shl vec, 3 ;Multiply by 8 + lea tmp, [mul_array + vec_i] + vbroadcastf32x2 xgft1, [tmp] + vbroadcastf32x2 xgft2, [tmp + vec] + vbroadcastf32x2 xgft3, [tmp + vec*2] + mov dest2, [dest1 + 8] ; reuse mul_array + mov dest3, [dest1 + 2*8] ; reuse vec + mov dest1, [dest1] + +.loop64: + ENCODE_64B_3 + + add pos, 64 ;Loop on 64 bytes at a time + sub len, 64 + cmp len, 64 + jge .loop64 + +.len_lt_64: + cmp len, 0 + jle .exit + + xor tmp, tmp + bts tmp, len + dec tmp + kmovq k1, tmp + + ENCODE_64B_3 k1 + +.exit: + vzeroupper + + FUNC_RESTORE + ret + +endproc_frame +%endif ; if AS_FEATURE_LEVEL >= 10 diff --git a/erasure_code/gf_4vect_mad_avx512_gfni.asm b/erasure_code/gf_4vect_mad_avx512_gfni.asm new file mode 100644 index 0000000..011b39c --- /dev/null +++ b/erasure_code/gf_4vect_mad_avx512_gfni.asm @@ -0,0 +1,221 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright(c) 2023 Intel Corporation All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in +; the documentation and/or other materials provided with the +; distribution. +; * Neither the name of Intel Corporation nor the names of its +; contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +;;; +;;; gf_4vect_mad_avx512_gfni(len, vec, vec_i, mul_array, src, dest); +;;; + +%include "reg_sizes.asm" +%include "gf_vect_gfni.inc" + +%if AS_FEATURE_LEVEL >= 10 + +%ifidn __OUTPUT_FORMAT__, elf64 + %define arg0 rdi + %define arg1 rsi + %define arg2 rdx + %define arg3 rcx + %define arg4 r8 + %define arg5 r9 + %define tmp r11 + %define func(x) x: endbranch + %define FUNC_SAVE + %define FUNC_RESTORE +%endif + +%ifidn __OUTPUT_FORMAT__, win64 + %define arg0 rcx + %define arg1 rdx + %define arg2 r8 + %define arg3 r9 + %define arg4 r12 + %define arg5 r13 + %define tmp r11 + %define stack_size 7*16 + 3*8 + %define arg(x) [rsp + stack_size + 8 + 8*x] + %define func(x) proc_frame x + +%macro FUNC_SAVE 0 + sub rsp, stack_size + vmovdqa [rsp + 16*0], xmm6 + vmovdqa [rsp + 16*1], xmm7 + vmovdqa [rsp + 16*2], xmm8 + vmovdqa [rsp + 16*3], xmm9 + vmovdqa [rsp + 16*4], xmm10 + vmovdqa [rsp + 16*5], xmm11 + vmovdqa [rsp + 16*6], xmm12 + mov [rsp + 7*16 + 0*8], r12 + mov [rsp + 7*16 + 1*8], r13 + end_prolog + mov arg4, arg(4) + mov arg5, arg(5) +%endmacro + +%macro FUNC_RESTORE 0 + vmovdqa xmm6, [rsp + 16*0] + vmovdqa xmm7, [rsp + 16*1] + vmovdqa xmm8, [rsp + 16*2] + vmovdqa xmm9, [rsp + 16*3] + vmovdqa xmm10, [rsp + 16*4] + vmovdqa xmm11, [rsp + 16*5] + vmovdqa xmm12, [rsp + 16*6] + mov r12, [rsp + 7*16 + 0*8] + mov r13, [rsp + 7*16 + 1*8] + add rsp, stack_size +%endmacro +%endif + +%define len arg0 +%define vec arg1 +%define vec_i arg2 +%define mul_array arg3 +%define src arg4 +%define dest1 arg5 +%define pos rax +%define dest2 mul_array +%define dest3 vec +%define dest4 vec_i + +%ifndef EC_ALIGNED_ADDR +;;; Use Un-aligned load/store + %define XLDR vmovdqu8 + %define XSTR vmovdqu8 +%else +;;; Use Non-temporal load/stor + %ifdef NO_NT_LDST + %define XLDR vmovdqa64 + %define XSTR vmovdqa64 + %else + %define XLDR vmovntdqa + %define XSTR vmovntdq + %endif +%endif + +default rel +[bits 64] +section .text + +%define x0 zmm0 +%define xd1 zmm1 +%define xd2 zmm2 +%define xd3 zmm3 +%define xd4 zmm4 + +%define xgft1 zmm5 +%define xgft2 zmm6 +%define xgft3 zmm7 +%define xgft4 zmm8 + +%define xret1 zmm9 +%define xret2 zmm10 +%define xret3 zmm11 +%define xret4 zmm12 + +;; +;; Encodes 64 bytes of a single source into 4x 64 bytes (parity disks) +;; +%macro ENCODE_64B_4 0-1 +%define %%KMASK %1 + +%if %0 == 1 + vmovdqu8 x0{%%KMASK}, [src + pos] ;Get next source vector + vmovdqu8 xd1{%%KMASK}, [dest1 + pos] ;Get next dest vector + vmovdqu8 xd2{%%KMASK}, [dest2 + pos] ;Get next dest vector + vmovdqu8 xd3{%%KMASK}, [dest3 + pos] ;Get next dest vector + vmovdqu8 xd4{%%KMASK}, [dest4 + pos] ;Get next dest vector +%else + XLDR x0, [src + pos] ;Get next source vector + XLDR xd1, [dest1 + pos] ;Get next dest vector + XLDR xd2, [dest2 + pos] ;Get next dest vector + XLDR xd3, [dest3 + pos] ;Get next dest vector + XLDR xd4, [dest4 + pos] ;Get next dest vector +%endif + + GF_MUL_XOR x0, xgft1, xret1, xd1, xgft2, xret2, xd2, xgft3, xret3, xd3, \ + xgft4, xret4, xd4 + +%if %0 == 1 + vmovdqu8 [dest1 + pos]{%%KMASK}, xd1 + vmovdqu8 [dest2 + pos]{%%KMASK}, xd2 + vmovdqu8 [dest3 + pos]{%%KMASK}, xd3 + vmovdqu8 [dest4 + pos]{%%KMASK}, xd4 +%else + XSTR [dest1 + pos], xd1 + XSTR [dest2 + pos], xd2 + XSTR [dest3 + pos], xd3 + XSTR [dest4 + pos], xd4 +%endif +%endmacro + +align 16 +mk_global gf_4vect_mad_avx512_gfni, function +func(gf_4vect_mad_avx512_gfni) + FUNC_SAVE + + xor pos, pos + shl vec_i, 3 ;Multiply by 8 + shl vec, 3 ;Multiply by 8 + lea tmp, [mul_array + vec_i] + vbroadcastf32x2 xgft1, [tmp] + vbroadcastf32x2 xgft2, [tmp + vec] + vbroadcastf32x2 xgft3, [tmp + vec*2] + add tmp, vec + vbroadcastf32x2 xgft4, [tmp + vec*2] + mov dest2, [dest1 + 8] ; reuse mul_array + mov dest3, [dest1 + 2*8] ; reuse vec + mov dest4, [dest1 + 3*8] ; reuse vec_i + mov dest1, [dest1] + +.loop64: + ENCODE_64B_4 + + add pos, 64 ;Loop on 64 bytes at a time + sub len, 64 + cmp len, 64 + jge .loop64 + +.len_lt_64: + cmp len, 0 + jle .exit + + xor tmp, tmp + bts tmp, len + dec tmp + kmovq k1, tmp + + ENCODE_64B_4 k1 + +.exit: + vzeroupper + + FUNC_RESTORE + ret + +endproc_frame +%endif ; if AS_FEATURE_LEVEL >= 10 diff --git a/erasure_code/gf_5vect_mad_avx512_gfni.asm b/erasure_code/gf_5vect_mad_avx512_gfni.asm new file mode 100644 index 0000000..bcea47a --- /dev/null +++ b/erasure_code/gf_5vect_mad_avx512_gfni.asm @@ -0,0 +1,238 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright(c) 2023 Intel Corporation All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in +; the documentation and/or other materials provided with the +; distribution. +; * Neither the name of Intel Corporation nor the names of its +; contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +;;; +;;; gf_5vect_mad_avx512_gfni(len, vec, vec_i, mul_array, src, dest); +;;; + +%include "reg_sizes.asm" +%include "gf_vect_gfni.inc" + +%if AS_FEATURE_LEVEL >= 10 + +%ifidn __OUTPUT_FORMAT__, elf64 + %define arg0 rdi + %define arg1 rsi + %define arg2 rdx + %define arg3 rcx + %define arg4 r8 + %define arg5 r9 + %define tmp r11 + %define tmp2 r10 + %define func(x) x: endbranch + %define FUNC_SAVE + %define FUNC_RESTORE +%endif + +%ifidn __OUTPUT_FORMAT__, win64 + %define arg0 rcx + %define arg1 rdx + %define arg2 r8 + %define arg3 r9 + %define arg4 r12 + %define arg5 r13 + %define tmp r11 + %define tmp2 r10 + %define stack_size 16*10 + 3*8 + %define arg(x) [rsp + stack_size + 8 + 8*x] + %define func(x) proc_frame x + +%macro FUNC_SAVE 0 + sub rsp, stack_size + vmovdqa [rsp + 16*0], xmm6 + vmovdqa [rsp + 16*1], xmm7 + vmovdqa [rsp + 16*2], xmm8 + vmovdqa [rsp + 16*3], xmm9 + vmovdqa [rsp + 16*4], xmm10 + vmovdqa [rsp + 16*5], xmm11 + vmovdqa [rsp + 16*6], xmm12 + vmovdqa [rsp + 16*7], xmm13 + vmovdqa [rsp + 16*8], xmm14 + vmovdqa [rsp + 16*9], xmm15 + mov [rsp + 10*16 + 0*8], r12 + mov [rsp + 10*16 + 1*8], r13 + end_prolog + mov arg4, arg(4) + mov arg5, arg(5) +%endmacro + +%macro FUNC_RESTORE 0 + vmovdqa xmm6, [rsp + 16*0] + vmovdqa xmm7, [rsp + 16*1] + vmovdqa xmm8, [rsp + 16*2] + vmovdqa xmm9, [rsp + 16*3] + vmovdqa xmm10, [rsp + 16*4] + vmovdqa xmm11, [rsp + 16*5] + vmovdqa xmm12, [rsp + 16*6] + vmovdqa xmm13, [rsp + 16*7] + vmovdqa xmm14, [rsp + 16*8] + vmovdqa xmm15, [rsp + 16*9] + mov r12, [rsp + 10*16 + 0*8] + mov r13, [rsp + 10*16 + 1*8] + add rsp, stack_size +%endmacro +%endif + +%define len arg0 +%define vec arg1 +%define vec_i arg2 +%define mul_array arg3 +%define src arg4 +%define dest1 arg5 +%define pos rax +%define dest2 tmp2 +%define dest3 mul_array +%define dest4 vec +%define dest5 vec_i + +%ifndef EC_ALIGNED_ADDR +;;; Use Un-aligned load/store + %define XLDR vmovdqu8 + %define XSTR vmovdqu8 +%else +;;; Use Non-temporal load/stor + %ifdef NO_NT_LDST + %define XLDR vmovdqa64 + %define XSTR vmovdqa64 + %else + %define XLDR vmovntdqa + %define XSTR vmovntdq + %endif +%endif + +default rel +[bits 64] +section .text + +%define x0 zmm0 +%define xd1 zmm1 +%define xd2 zmm2 +%define xd3 zmm3 +%define xd4 zmm4 +%define xd5 zmm5 + +%define xgft1 zmm6 +%define xgft2 zmm7 +%define xgft3 zmm8 +%define xgft4 zmm9 +%define xgft5 zmm10 + +%define xret1 zmm11 +%define xret2 zmm12 +%define xret3 zmm13 +%define xret4 zmm14 +%define xret5 zmm15 + +;; +;; Encodes 64 bytes of a single source into 5x 64 bytes (parity disks) +;; +%macro ENCODE_64B_5 0-1 +%define %%KMASK %1 + +%if %0 == 1 + vmovdqu8 x0{%%KMASK}, [src + pos] ;Get next source vector + vmovdqu8 xd1{%%KMASK}, [dest1 + pos] ;Get next dest vector + vmovdqu8 xd2{%%KMASK}, [dest2 + pos] ;Get next dest vector + vmovdqu8 xd3{%%KMASK}, [dest3 + pos] ;Get next dest vector + vmovdqu8 xd4{%%KMASK}, [dest4 + pos] ;Get next dest vector + vmovdqu8 xd5{%%KMASK}, [dest5 + pos] ;Get next dest vector +%else + XLDR x0, [src + pos] ;Get next source vector + XLDR xd1, [dest1 + pos] ;Get next dest vector + XLDR xd2, [dest2 + pos] ;Get next dest vector + XLDR xd3, [dest3 + pos] ;Get next dest vector + XLDR xd4, [dest4 + pos] ;Get next dest vector + XLDR xd5, [dest5 + pos] ;Get next dest vector +%endif + + GF_MUL_XOR x0, xgft1, xret1, xd1, xgft2, xret2, xd2, xgft3, xret3, xd3, \ + xgft4, xret4, xd4, xgft5, xret5, xd5 + +%if %0 == 1 + vmovdqu8 [dest1 + pos]{%%KMASK}, xd1 + vmovdqu8 [dest2 + pos]{%%KMASK}, xd2 + vmovdqu8 [dest3 + pos]{%%KMASK}, xd3 + vmovdqu8 [dest4 + pos]{%%KMASK}, xd4 + vmovdqu8 [dest5 + pos]{%%KMASK}, xd5 +%else + XSTR [dest1 + pos], xd1 + XSTR [dest2 + pos], xd2 + XSTR [dest3 + pos], xd3 + XSTR [dest4 + pos], xd4 + XSTR [dest5 + pos], xd5 +%endif +%endmacro +align 16 +mk_global gf_5vect_mad_avx512_gfni, function +func(gf_5vect_mad_avx512_gfni) + FUNC_SAVE + + xor pos, pos + shl vec_i, 3 ;Multiply by 8 + shl vec, 3 ;Multiply by 8 + lea tmp, [mul_array + vec_i] + vbroadcastf32x2 xgft1, [tmp] + vbroadcastf32x2 xgft2, [tmp + vec] + vbroadcastf32x2 xgft3, [tmp + vec*2] + vbroadcastf32x2 xgft5, [tmp + vec*4] + add tmp, vec + vbroadcastf32x2 xgft4, [tmp + vec*2] + mov dest2, [dest1 + 8] + mov dest3, [dest1 + 2*8] ; reuse mul_array + mov dest4, [dest1 + 3*8] ; reuse vec + mov dest5, [dest1 + 4*8] ; reuse vec_i + mov dest1, [dest1] + +.loop64: + ENCODE_64B_5 + + add pos, 64 ;Loop on 64 bytes at a time + sub len, 64 + cmp len, 64 + jge .loop64 + +.len_lt_64: + cmp len, 0 + jle .exit + + xor tmp, tmp + bts tmp, len + dec tmp + kmovq k1, tmp + + ENCODE_64B_5 k1 + +.exit: + vzeroupper + + FUNC_RESTORE + ret + +endproc_frame +%endif ; if AS_FEATURE_LEVEL >= 10 diff --git a/erasure_code/gf_6vect_mad_avx512_gfni.asm b/erasure_code/gf_6vect_mad_avx512_gfni.asm new file mode 100644 index 0000000..3641183 --- /dev/null +++ b/erasure_code/gf_6vect_mad_avx512_gfni.asm @@ -0,0 +1,257 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright(c) 2023 Intel Corporation All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in +; the documentation and/or other materials provided with the +; distribution. +; * Neither the name of Intel Corporation nor the names of its +; contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +;;; +;;; gf_6vect_mad_avx512_gfni(len, vec, vec_i, mul_array, src, dest); +;;; + +%include "reg_sizes.asm" +%include "gf_vect_gfni.inc" + +%if AS_FEATURE_LEVEL >= 10 + +%ifidn __OUTPUT_FORMAT__, elf64 + %define arg0 rdi + %define arg1 rsi + %define arg2 rdx + %define arg3 rcx + %define arg4 r8 + %define arg5 r9 + %define tmp r11 + %define tmp2 r10 + %define tmp3 r12 ;must be saved and restored + %define func(x) x: endbranch + %macro FUNC_SAVE 0 + push r12 + %endmacro + %macro FUNC_RESTORE 0 + pop r12 + %endmacro +%endif + +%ifidn __OUTPUT_FORMAT__, win64 + %define arg0 rcx + %define arg1 rdx + %define arg2 r8 + %define arg3 r9 + %define arg4 r12 + %define arg5 r14 + %define tmp r11 + %define tmp2 r10 + %define tmp3 r13 + %define stack_size 16*10 + 3*8 + %define arg(x) [rsp + stack_size + 8 + 8*x] + %define func(x) proc_frame x + +%macro FUNC_SAVE 0 + sub rsp, stack_size + vmovdqa [rsp + 16*0], xmm6 + vmovdqa [rsp + 16*1], xmm7 + vmovdqa [rsp + 16*2], xmm8 + vmovdqa [rsp + 16*3], xmm9 + vmovdqa [rsp + 16*4], xmm10 + vmovdqa [rsp + 16*5], xmm11 + vmovdqa [rsp + 16*6], xmm12 + vmovdqa [rsp + 16*7], xmm13 + vmovdqa [rsp + 16*8], xmm14 + vmovdqa [rsp + 16*9], xmm15 + mov [rsp + 10*16 + 0*8], r12 + mov [rsp + 10*16 + 1*8], r13 + mov [rsp + 10*16 + 2*8], r14 + end_prolog + mov arg4, arg(4) + mov arg5, arg(5) +%endmacro + +%macro FUNC_RESTORE 0 + vmovdqa xmm6, [rsp + 16*0] + vmovdqa xmm7, [rsp + 16*1] + vmovdqa xmm8, [rsp + 16*2] + vmovdqa xmm9, [rsp + 16*3] + vmovdqa xmm10, [rsp + 16*4] + vmovdqa xmm11, [rsp + 16*5] + vmovdqa xmm12, [rsp + 16*6] + vmovdqa xmm13, [rsp + 16*7] + vmovdqa xmm14, [rsp + 16*8] + vmovdqa xmm15, [rsp + 16*9] + mov r12, [rsp + 10*16 + 0*8] + mov r13, [rsp + 10*16 + 1*8] + mov r14, [rsp + 10*16 + 2*8] + add rsp, stack_size +%endmacro +%endif + +%define len arg0 +%define vec arg1 +%define vec_i arg2 +%define mul_array arg3 +%define src arg4 +%define dest1 arg5 +%define pos rax +%define dest2 tmp3 +%define dest3 tmp2 +%define dest4 mul_array +%define dest5 vec +%define dest6 vec_i + +%ifndef EC_ALIGNED_ADDR +;;; Use Un-aligned load/store + %define XLDR vmovdqu8 + %define XSTR vmovdqu8 +%else +;;; Use Non-temporal load/stor + %ifdef NO_NT_LDST + %define XLDR vmovdqa64 + %define XSTR vmovdqa64 + %else + %define XLDR vmovntdqa + %define XSTR vmovntdq + %endif +%endif + +default rel +[bits 64] +section .text + +%define x0 zmm0 +%define xd1 zmm1 +%define xd2 zmm2 +%define xd3 zmm3 +%define xd4 zmm4 +%define xd5 zmm5 +%define xd6 zmm6 + +%define xgft1 zmm7 +%define xgft2 zmm8 +%define xgft3 zmm9 +%define xgft4 zmm10 +%define xgft5 zmm11 +%define xgft6 zmm12 + +%define xret1 zmm13 +%define xret2 zmm14 +%define xret3 zmm15 +%define xret4 zmm16 +%define xret5 zmm17 +%define xret6 zmm18 + +;; +;; Encodes 64 bytes of a single source into 6x 64 bytes (parity disks) +;; +%macro ENCODE_64B_6 0-1 +%define %%KMASK %1 + +%if %0 == 1 + vmovdqu8 x0{%%KMASK}, [src + pos] ;Get next source vector + vmovdqu8 xd1{%%KMASK}, [dest1 + pos] ;Get next dest vector + vmovdqu8 xd2{%%KMASK}, [dest2 + pos] ;Get next dest vector + vmovdqu8 xd3{%%KMASK}, [dest3 + pos] ;Get next dest vector + vmovdqu8 xd4{%%KMASK}, [dest4 + pos] ;Get next dest vector + vmovdqu8 xd5{%%KMASK}, [dest5 + pos] ;Get next dest vector + vmovdqu8 xd6{%%KMASK}, [dest6 + pos] ;Get next dest vector +%else + XLDR x0, [src + pos] ;Get next source vector + XLDR xd1, [dest1 + pos] ;Get next dest vector + XLDR xd2, [dest2 + pos] ;Get next dest vector + XLDR xd3, [dest3 + pos] ;Get next dest vector + XLDR xd4, [dest4 + pos] ;Get next dest vector + XLDR xd5, [dest5 + pos] ;Get next dest vector + XLDR xd6, [dest6 + pos] ;Get next dest vector +%endif + + GF_MUL_XOR x0, xgft1, xret1, xd1, xgft2, xret2, xd2, xgft3, xret3, xd3, \ + xgft4, xret4, xd4, xgft5, xret5, xd5, xgft6, xret6, xd6 + +%if %0 == 1 + vmovdqu8 [dest1 + pos]{%%KMASK}, xd1 + vmovdqu8 [dest2 + pos]{%%KMASK}, xd2 + vmovdqu8 [dest3 + pos]{%%KMASK}, xd3 + vmovdqu8 [dest4 + pos]{%%KMASK}, xd4 + vmovdqu8 [dest5 + pos]{%%KMASK}, xd5 + vmovdqu8 [dest6 + pos]{%%KMASK}, xd6 +%else + XSTR [dest1 + pos], xd1 + XSTR [dest2 + pos], xd2 + XSTR [dest3 + pos], xd3 + XSTR [dest4 + pos], xd4 + XSTR [dest5 + pos], xd5 + XSTR [dest6 + pos], xd6 +%endif +%endmacro + +align 16 +mk_global gf_6vect_mad_avx512_gfni, function +func(gf_6vect_mad_avx512_gfni) + FUNC_SAVE + + xor pos, pos + shl vec_i, 3 ;Multiply by 8 + shl vec, 3 ;Multiply by 8 + lea tmp, [mul_array + vec_i] + vbroadcastf32x2 xgft1, [tmp] + vbroadcastf32x2 xgft2, [tmp + vec] + vbroadcastf32x2 xgft3, [tmp + vec*2] + vbroadcastf32x2 xgft5, [tmp + vec*4] + add tmp, vec + vbroadcastf32x2 xgft4, [tmp + vec*2] + vbroadcastf32x2 xgft6, [tmp + vec*4] + mov dest2, [dest1 + 8] + mov dest3, [dest1 + 2*8] + mov dest4, [dest1 + 3*8] ; reuse mul_array + mov dest5, [dest1 + 4*8] ; reuse vec + mov dest6, [dest1 + 5*8] ; reuse vec_i + mov dest1, [dest1] + +.loop64: + ENCODE_64B_6 + + add pos, 64 ;Loop on 64 bytes at a time + sub len, 64 + cmp len, 64 + jge .loop64 + +.len_lt_64: + cmp len, 0 + jle .exit + + xor tmp, tmp + bts tmp, len + dec tmp + kmovq k1, tmp + + ENCODE_64B_6 k1 + +.exit: + vzeroupper + + FUNC_RESTORE + ret + +endproc_frame +%endif ; if AS_FEATURE_LEVEL >= 10 diff --git a/erasure_code/gf_vect_mad_avx512_gfni.asm b/erasure_code/gf_vect_mad_avx512_gfni.asm new file mode 100644 index 0000000..1c96fcd --- /dev/null +++ b/erasure_code/gf_vect_mad_avx512_gfni.asm @@ -0,0 +1,173 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright(c) 2023 Intel Corporation All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in +; the documentation and/or other materials provided with the +; distribution. +; * Neither the name of Intel Corporation nor the names of its +; contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +;;; +;;; gf_vect_mad_avx512_gfni(len, vec, vec_i, mul_array, src, dest); +;;; + +%include "reg_sizes.asm" +%include "gf_vect_gfni.inc" + +%if AS_FEATURE_LEVEL >= 10 + +%ifidn __OUTPUT_FORMAT__, elf64 + %define arg0 rdi + %define arg1 rsi + %define arg2 rdx + %define arg3 rcx + %define arg4 r8 + %define arg5 r9 + %define tmp r11 + %define func(x) x: endbranch + %define FUNC_SAVE + %define FUNC_RESTORE +%endif + +%ifidn __OUTPUT_FORMAT__, win64 + %define arg0 rcx + %define arg1 rdx + %define arg2 r8 + %define arg3 r9 + %define arg4 r12 ; must be saved and loaded + %define arg5 r13 + %define tmp r11 + %define stack_size 3*8 + %define arg(x) [rsp + stack_size + 8 + 8*x] + %define func(x) proc_frame x + + %macro FUNC_SAVE 0 + sub rsp, stack_size + mov [rsp + 0*8], r12 + mov [rsp + 1*8], r13 + end_prolog + mov arg4, arg(4) + mov arg5, arg(5) + %endmacro + + %macro FUNC_RESTORE 0 + mov r12, [rsp + 0*8] + mov r13, [rsp + 1*8] + add rsp, stack_size + %endmacro +%endif + +;;; gf_vect_mad_avx512_gfni(len, vec, vec_i, mul_array, src, dest) +%define len arg0 +%define vec arg1 +%define vec_i arg2 +%define mul_array arg3 +%define src arg4 +%define dest arg5 +%define pos rax + +%ifndef EC_ALIGNED_ADDR +;;; Use Un-aligned load/store + %define XLDR vmovdqu8 + %define XSTR vmovdqu8 +%else +;;; Use Non-temporal load/stor + %ifdef NO_NT_LDST + %define XLDR vmovdqa64 + %define XSTR vmovdqa64 + %else + %define XLDR vmovntdqa + %define XSTR vmovntdq + %endif +%endif + + +default rel + +[bits 64] +section .text + +%define x0 zmm0 +%define xd zmm1 +%define xgft1 zmm2 +%define xret1 zmm3 + +;; +;; Encodes 64 bytes of a single source into 64 bytes (single parity disk) +;; +%macro ENCODE_64B 0-1 +%define %%KMASK %1 + +%if %0 == 1 + vmovdqu8 x0{%%KMASK}, [src + pos] ;Get next source vector + vmovdqu8 xd{%%KMASK}, [dest + pos] ;Get next dest vector +%else + XLDR x0, [src + pos] ;Get next source vector + XLDR xd, [dest + pos] ;Get next dest vector +%endif + + GF_MUL_XOR x0, xgft1, xret1, xd + +%if %0 == 1 + vmovdqu8 [dest + pos]{%%KMASK}, xd +%else + XSTR [dest + pos], xd +%endif +%endmacro + +align 16 +mk_global gf_vect_mad_avx512_gfni, function +func(gf_vect_mad_avx512_gfni) + FUNC_SAVE + xor pos, pos + shl vec_i, 3 ;Multiply by 8 + + vbroadcastf32x2 xgft1, [vec_i + mul_array] + +.loop64: + ENCODE_64B + + add pos, 64 ;Loop on 64 bytes at a time + sub len, 64 + cmp len, 64 + jge .loop64 + +.len_lt_64: + cmp len, 0 + jle .exit + + xor tmp, tmp + bts tmp, len + dec tmp + kmovq k1, tmp + + ENCODE_64B k1 + +.exit: + vzeroupper + + FUNC_RESTORE + ret + +endproc_frame +%endif ; if AS_FEATURE_LEVEL >= 10