mirror of
https://github.com/intel/isa-l.git
synced 2025-01-07 23:28:58 +01:00
igzip: Bitbuf improvements
Update Bitbuf to use stdmac and decrease register dependencies by replaces a sub with an and. Change-Id: Iaadf3c6ef7f533540a7adb57a418e9e80e9b8503 Signed-off-by: Roy Oursler <roy.j.oursler@intel.com>
This commit is contained in:
parent
53b92e83f4
commit
623d2f0dc0
@ -28,6 +28,7 @@
|
|||||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||||
|
|
||||||
%include "options.asm"
|
%include "options.asm"
|
||||||
|
%include "stdmac.asm"
|
||||||
|
|
||||||
; Assumes m_out_buf is a register
|
; Assumes m_out_buf is a register
|
||||||
; Clobbers RCX
|
; Clobbers RCX
|
||||||
@ -40,12 +41,8 @@
|
|||||||
%define %%count %4
|
%define %%count %4
|
||||||
%define %%m_out_buf %5
|
%define %%m_out_buf %5
|
||||||
|
|
||||||
%ifdef USE_HSWNI
|
SHLX %%code, %%code, %%m_bit_count
|
||||||
shlx %%code, %%code, %%m_bit_count
|
|
||||||
%else
|
|
||||||
mov rcx, %%m_bit_count
|
|
||||||
shl %%code, cl
|
|
||||||
%endif
|
|
||||||
or %%m_bits, %%code
|
or %%m_bits, %%code
|
||||||
add %%m_bit_count, %%count
|
add %%m_bit_count, %%count
|
||||||
|
|
||||||
@ -54,12 +51,9 @@
|
|||||||
shr rcx, 3 ; rcx = bytes
|
shr rcx, 3 ; rcx = bytes
|
||||||
add %%m_out_buf, rcx
|
add %%m_out_buf, rcx
|
||||||
shl rcx, 3 ; rcx = bits
|
shl rcx, 3 ; rcx = bits
|
||||||
sub %%m_bit_count, rcx
|
and %%m_bit_count, 0x7
|
||||||
%ifdef USE_HSWNI
|
|
||||||
shrx %%m_bits, %%m_bits, rcx
|
SHRX %%m_bits, %%m_bits, rcx
|
||||||
%else
|
|
||||||
shr %%m_bits, cl
|
|
||||||
%endif
|
|
||||||
%endm
|
%endm
|
||||||
|
|
||||||
%macro write_dword 2
|
%macro write_dword 2
|
||||||
|
Loading…
Reference in New Issue
Block a user