diff --git a/erasure_code/aarch64/gf_vect_mul_sve.S b/erasure_code/aarch64/gf_vect_mul_sve.S
index d52fb17..d2219bf 100644
--- a/erasure_code/aarch64/gf_vect_mul_sve.S
+++ b/erasure_code/aarch64/gf_vect_mul_sve.S
@@ -53,12 +53,13 @@ x_len		.req	x0
 x_tbl		.req	x1
 x_src		.req	x2
 x_dest		.req	x3
+x_tmp		.req	x4
 
 /* returns */
 w_ret		.req	w0
 
 /* local variables */
-x_pos		.req	x4
+x_pos		.req	x5
 
 /* vectors */
 z_mask0f	.req	z0
@@ -77,9 +78,10 @@ q_gft1_lo	.req	q6
 q_gft1_hi	.req	q7
 
 cdecl(gf_vect_mul_sve):
-	/* less than 32 bytes, return_fail */
-	cmp	x_len, #32
-	blt	.return_fail
+	/* len not aligned to 32B, return_fail */
+	and	x_tmp, x_len, #0x1f
+	cmp	x_tmp, #0
+	bne	.return_fail
 
 	mov	z_mask0f.b, #0x0f		/* z_mask0f = 0x0F0F...0F */
 	mov	x_pos, #0
diff --git a/erasure_code/gf_vect_mul_test.c b/erasure_code/gf_vect_mul_test.c
index b00f4d3..80eee18 100644
--- a/erasure_code/gf_vect_mul_test.c
+++ b/erasure_code/gf_vect_mul_test.c
@@ -171,7 +171,7 @@ int main(int argc, char *argv[])
 #endif
 	}
 
-#if !defined(aarch64) && !defined(ppc64le)
+#if !defined(ppc64le)
 	// Test all unsupported sizes up to TEST_SIZE
 	for (size = 0; size < TEST_SIZE; size++) {
 		if (size % align != 0 && gf_vect_mul(size, gf_const_tbl, buff1, buff2) == 0) {
@@ -183,7 +183,7 @@ int main(int argc, char *argv[])
 	}
 #else
 	printf
-	    ("WARNING: Test disabled on ARM & PPC due to known issue https://github.com/intel/isa-l/issues/263\n");
+	    ("WARNING: Test disabled on PPC due to known issue https://github.com/intel/isa-l/issues/263\n");
 #endif
 	printf(" done: Pass\n");
 	fflush(0);