mirror of
https://github.com/intel/isa-l.git
synced 2024-12-13 09:52:56 +01:00
181 lines
4.6 KiB
NASM
181 lines
4.6 KiB
NASM
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; * Neither the name of Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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default rel
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[bits 64]
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%ifidn __OUTPUT_FORMAT__, elf64
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%define WRT_OPT wrt ..plt
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%else
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%define WRT_OPT
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%endif
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%include "reg_sizes.asm"
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extern crc32_iscsi_00
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extern crc32_iscsi_01
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extern crc32_iscsi_base
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extern crc32_ieee_01
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extern crc32_ieee_by4 ;; Optimized for SLM
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extern crc32_ieee_base
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extern crc16_t10dif_01
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extern crc16_t10dif_by4 ;; Optimized for SLM
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extern crc16_t10dif_base
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section .data
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;;; *_mbinit are initial values for *_dispatched; is updated on first call.
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;;; Therefore, *_dispatch_init is only executed on first call.
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crc32_iscsi_dispatched:
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dq crc32_iscsi_mbinit
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crc32_ieee_dispatched:
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dq crc32_ieee_mbinit
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crc16_t10dif_dispatched:
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dq crc16_t10dif_mbinit
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section .text
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;;;;
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; crc32_iscsi multibinary function
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;;;;
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global crc32_iscsi:function
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crc32_iscsi_mbinit:
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call crc32_iscsi_dispatch_init
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crc32_iscsi:
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jmp qword [crc32_iscsi_dispatched]
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crc32_iscsi_dispatch_init:
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push rax
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push rbx
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push rcx
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push rdx
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push rsi
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lea rsi, [crc32_iscsi_base WRT_OPT] ; Default
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mov eax, 1
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cpuid
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lea rbx, [crc32_iscsi_00 WRT_OPT]
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lea rax, [crc32_iscsi_01 WRT_OPT]
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test ecx, FLAG_CPUID1_ECX_SSE4_2
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cmovne rsi, rbx
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test ecx, FLAG_CPUID1_ECX_CLMUL
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cmovne rsi, rax
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mov [crc32_iscsi_dispatched], rsi
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pop rsi
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pop rdx
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pop rcx
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pop rbx
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pop rax
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ret
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;;;;
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; crc32_ieee multibinary function
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;;;;
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global crc32_ieee:function
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crc32_ieee_mbinit:
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call crc32_ieee_dispatch_init
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crc32_ieee:
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jmp qword [crc32_ieee_dispatched]
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crc32_ieee_dispatch_init:
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push rax
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push rbx
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push rcx
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push rdx
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push rsi
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lea rsi, [crc32_ieee_base WRT_OPT] ; Default
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mov eax, 1
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cpuid
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lea rbx, [crc32_ieee_01 WRT_OPT]
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lea rdx, [crc32_ieee_by4 WRT_OPT]
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test ecx, FLAG_CPUID1_ECX_SSE3
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jz use_ieee_base
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test ecx, FLAG_CPUID1_ECX_CLMUL
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cmovne rsi, rbx
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and eax, FLAG_CPUID1_EAX_STEP_MASK
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cmp eax, FLAG_CPUID1_EAX_AVOTON
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cmove rsi, rdx
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use_ieee_base:
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mov [crc32_ieee_dispatched], rsi
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pop rsi
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pop rdx
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pop rcx
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pop rbx
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pop rax
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ret
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;;;;
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; crc16_t10dif multibinary function
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;;;;
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global crc16_t10dif:function
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crc16_t10dif_mbinit:
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call crc16_t10dif_dispatch_init
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crc16_t10dif:
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jmp qword [crc16_t10dif_dispatched]
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crc16_t10dif_dispatch_init:
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push rax
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push rbx
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push rcx
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push rdx
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push rsi
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lea rsi, [crc16_t10dif_base WRT_OPT] ; Default
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mov eax, 1
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cpuid
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lea rbx, [crc16_t10dif_01 WRT_OPT]
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lea rdx, [crc16_t10dif_by4 WRT_OPT]
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test ecx, FLAG_CPUID1_ECX_SSE3
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jz use_t10dif_base
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test ecx, FLAG_CPUID1_ECX_CLMUL
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cmovne rsi, rbx
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and eax, FLAG_CPUID1_EAX_STEP_MASK
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cmp eax, FLAG_CPUID1_EAX_AVOTON
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cmove rsi, rdx
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use_t10dif_base:
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mov [crc16_t10dif_dispatched], rsi
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pop rsi
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pop rdx
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pop rcx
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pop rbx
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pop rax
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ret
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;;; func core, ver, snum
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slversion crc16_t10dif, 00, 03, 011a
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slversion crc32_ieee, 00, 03, 011b
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slversion crc32_iscsi, 00, 03, 011c
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