2019-10-25 03:18:08 +02:00
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##################################################################
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# Copyright (c) 2019 Huawei Technologies Co., Ltd.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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# * Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# * Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in
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# the documentation and/or other materials provided with the
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# distribution.
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# * Neither the name of Huawei Corporation nor the names of its
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# contributors may be used to endorse or promote products derived
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# from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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########################################################################
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lsrc_aarch64 += \
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erasure_code/aarch64/ec_aarch64_highlevel_func.c \
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erasure_code/aarch64/ec_aarch64_dispatcher.c \
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erasure_code/aarch64/gf_vect_dot_prod_neon.S \
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erasure_code/aarch64/gf_2vect_dot_prod_neon.S \
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erasure_code/aarch64/gf_3vect_dot_prod_neon.S \
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erasure_code/aarch64/gf_4vect_dot_prod_neon.S \
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erasure_code/aarch64/gf_5vect_dot_prod_neon.S \
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erasure_code/aarch64/gf_vect_mad_neon.S \
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erasure_code/aarch64/gf_2vect_mad_neon.S \
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erasure_code/aarch64/gf_3vect_mad_neon.S \
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erasure_code/aarch64/gf_4vect_mad_neon.S \
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erasure_code/aarch64/gf_5vect_mad_neon.S \
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erasure_code/aarch64/gf_6vect_mad_neon.S \
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erasure_code/aarch64/gf_vect_mul_neon.S \
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Enable SVE in ISA-L erasure code for aarch64
This patch adds Arm (aarch64) SVE [1] variable-length vector assembly support
into ISA-L erasure code library. "Arm designed the Scalable Vector Extension
(SVE) as a next-generation SIMD extension to AArch64. SVE allows flexible
vector length implementations with a range of possible values in CPU
implementations. The vector length can vary from a minimum of 128 bits up to
a maximum of 2048 bits, at 128-bit increments. The SVE design guarantees
that the same application can run on different implementations that support
SVE, without the need to recompile the code. " [3]
Test method:
- This patch was tested on Fujitsu's A64FX [2], and it passed all erasure
code related test cases, including "make checks" , "make test", and
"make perf".
- To ensure code testing coverage, parameters in files (erasure_code/
erasure_code_test.c , erasure_code_update_test.c and gf_vect_mad_test.c)
are modified to cover all _vect versions of _mad_sve() / _dot_prod_sve()
rutines.
Performance improvements over NEON:
In general, SVE benchmarks (bandwidth in MB/s) are 40% ~ 100% higher than NEON
when running _cold style (data uncached and pulled from memory) perfs. This
includes routines of dot_prod, mad, and mul.
Optimization points:
This patch was tuned for the best performance on A64FX. Tuning points being
touched in this patch include:
1) Data prefetch into L2 cache before loading. See _sve.S files.
2) Instruction sequence orchestration. Such as interleaving every two
'ld1b/st1b' instructions with other instructions. See _sve.S files.
3) To improve dest vectors parallelism, in highlevel, running
gf_4vect_dot_prod_sve twice is better than running gf_8vect_dot_prod_sve()
once, and it's also better than running _7vect + _vect, _6vect + _2vect,
and _5vect + _3vect. The similar idea is applied to improve 11 ~ 9 dest
vectors dot product computing as well. The related change can be found
in ec_encode_data_sve() of file:
erasure_code/aarch64/ec_aarch64_highlevel_func.c
Notes:
1) About vector length: A64FX has a vector register length of 512bit. However,
this patchset was written with variable length assembly so it work
automatically on aarch64 machines with any types of SVE vector length,
such as SVE-128, SVE-256, etc..
2) About optimization: Due to differences in microarchitecture and
cache/memory design, to achieve optimum performance on SVE capable CPUs
other than A64FX, it is considered necessary to do microarchitecture-level
tunings on these CPUs.
[1] Introduction to SVE - Arm Developer.
https://developer.arm.com/documentation/102476/latest/
[2] FUJITSU Processor A64FX.
https://www.fujitsu.com/global/products/computing/servers/supercomputer/a64fx/
[3] Introducing SVE.
https://developer.arm.com/documentation/102476/0001/Introducing-SVE
Change-Id: If49eb8a956154d799dcda0ba4c9c6d979f5064a9
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
2021-12-28 10:32:39 +01:00
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erasure_code/aarch64/gf_vect_mad_sve.S \
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erasure_code/aarch64/gf_2vect_mad_sve.S \
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erasure_code/aarch64/gf_3vect_mad_sve.S \
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erasure_code/aarch64/gf_4vect_mad_sve.S \
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erasure_code/aarch64/gf_5vect_mad_sve.S \
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erasure_code/aarch64/gf_6vect_mad_sve.S \
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erasure_code/aarch64/gf_vect_dot_prod_sve.S \
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erasure_code/aarch64/gf_2vect_dot_prod_sve.S \
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erasure_code/aarch64/gf_3vect_dot_prod_sve.S \
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erasure_code/aarch64/gf_4vect_dot_prod_sve.S \
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erasure_code/aarch64/gf_5vect_dot_prod_sve.S \
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erasure_code/aarch64/gf_6vect_dot_prod_sve.S \
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erasure_code/aarch64/gf_7vect_dot_prod_sve.S \
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erasure_code/aarch64/gf_8vect_dot_prod_sve.S \
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erasure_code/aarch64/gf_vect_mul_sve.S \
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2019-10-25 03:18:08 +02:00
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erasure_code/aarch64/ec_multibinary_arm.S
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