385 lines
10 KiB
NASM
385 lines
10 KiB
NASM
; /*
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; * Provide SIMD optimizations for transform_add functions for HEVC decoding
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; * Copyright (c) 2014 Pierre-Edouard LEPERE
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; *
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; * This file is part of FFmpeg.
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; *
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; * FFmpeg is free software; you can redistribute it and/or
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; * modify it under the terms of the GNU Lesser General Public
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; * License as published by the Free Software Foundation; either
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; * version 2.1 of the License, or (at your option) any later version.
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; *
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; * FFmpeg is distributed in the hope that it will be useful,
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; * but WITHOUT ANY WARRANTY; without even the implied warranty of
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; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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; * Lesser General Public License for more details.
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; *
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; * You should have received a copy of the GNU Lesser General Public
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; * License along with FFmpeg; if not, write to the Free Software
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; * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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; */
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%include "libavutil/x86/x86util.asm"
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SECTION_RODATA 32
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max_pixels_10: times 16 dw ((1 << 10)-1)
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SECTION .text
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;the tr_add macros and functions were largely inspired by x264 project's code in the h264_idct.asm file
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%macro TR_ADD_MMX_4_8 0
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mova m2, [r1]
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mova m4, [r1+8]
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pxor m3, m3
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psubw m3, m2
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packuswb m2, m2
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packuswb m3, m3
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pxor m5, m5
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psubw m5, m4
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packuswb m4, m4
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packuswb m5, m5
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movh m0, [r0 ]
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movh m1, [r0+r2 ]
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paddusb m0, m2
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paddusb m1, m4
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psubusb m0, m3
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psubusb m1, m5
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movh [r0 ], m0
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movh [r0+r2 ], m1
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%endmacro
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INIT_MMX mmxext
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; void ff_hevc_tranform_add_8_mmxext(uint8_t *dst, int16_t *coeffs, ptrdiff_t stride)
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cglobal hevc_transform_add4_8, 3, 4, 6
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TR_ADD_MMX_4_8
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add r1, 16
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lea r0, [r0+r2*2]
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TR_ADD_MMX_4_8
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RET
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%macro TR_ADD_SSE_8_8 0
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pxor m3, m3
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mova m4, [r1]
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mova m6, [r1+16]
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mova m0, [r1+32]
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mova m2, [r1+48]
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psubw m5, m3, m4
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psubw m7, m3, m6
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psubw m1, m3, m0
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packuswb m4, m0
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packuswb m5, m1
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psubw m3, m2
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packuswb m6, m2
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packuswb m7, m3
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movq m0, [r0 ]
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movq m1, [r0+r2 ]
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movhps m0, [r0+r2*2]
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movhps m1, [r0+r3 ]
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paddusb m0, m4
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paddusb m1, m6
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psubusb m0, m5
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psubusb m1, m7
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movq [r0 ], m0
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movq [r0+r2 ], m1
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movhps [r0+2*r2], m0
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movhps [r0+r3 ], m1
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%endmacro
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%macro TR_ADD_INIT_SSE_8 0
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pxor m0, m0
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mova m4, [r1]
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mova m1, [r1+16]
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psubw m2, m0, m1
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psubw m5, m0, m4
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packuswb m4, m1
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packuswb m5, m2
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mova m6, [r1+32]
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mova m1, [r1+48]
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psubw m2, m0, m1
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psubw m7, m0, m6
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packuswb m6, m1
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packuswb m7, m2
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mova m8, [r1+64]
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mova m1, [r1+80]
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psubw m2, m0, m1
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psubw m9, m0, m8
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packuswb m8, m1
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packuswb m9, m2
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mova m10, [r1+96]
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mova m1, [r1+112]
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psubw m2, m0, m1
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psubw m11, m0, m10
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packuswb m10, m1
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packuswb m11, m2
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%endmacro
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%macro TR_ADD_SSE_16_8 0
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TR_ADD_INIT_SSE_8
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paddusb m0, m4, [r0 ]
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paddusb m1, m6, [r0+r2 ]
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paddusb m2, m8, [r0+r2*2]
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paddusb m3, m10,[r0+r3 ]
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psubusb m0, m5
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psubusb m1, m7
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psubusb m2, m9
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psubusb m3, m11
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mova [r0 ], m0
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mova [r0+r2 ], m1
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mova [r0+2*r2], m2
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mova [r0+r3 ], m3
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%endmacro
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%macro TR_ADD_SSE_32_8 0
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TR_ADD_INIT_SSE_8
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paddusb m0, m4, [r0 ]
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paddusb m1, m6, [r0+16 ]
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paddusb m2, m8, [r0+r2 ]
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paddusb m3, m10,[r0+r2+16]
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psubusb m0, m5
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psubusb m1, m7
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psubusb m2, m9
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psubusb m3, m11
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mova [r0 ], m0
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mova [r0+16 ], m1
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mova [r0+r2 ], m2
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mova [r0+r2+16], m3
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%endmacro
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INIT_XMM sse2
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; void ff_hevc_transform_add8_8_sse2(uint8_t *dst, int16_t *coeffs, ptrdiff_t stride)
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cglobal hevc_transform_add8_8, 3, 4, 8
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lea r3, [r2*3]
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TR_ADD_SSE_8_8
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add r1, 64
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lea r0, [r0+r2*4]
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TR_ADD_SSE_8_8
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RET
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%if ARCH_X86_64
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; void ff_hevc_transform_add16_8_sse2(uint8_t *dst, int16_t *coeffs, ptrdiff_t stride)
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cglobal hevc_transform_add16_8, 3, 4, 12
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lea r3, [r2*3]
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TR_ADD_SSE_16_8
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%rep 3
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add r1, 128
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lea r0, [r0+r2*4]
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TR_ADD_SSE_16_8
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%endrep
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RET
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; void ff_hevc_transform_add16_8_sse2(uint8_t *dst, int16_t *coeffs, ptrdiff_t stride)
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cglobal hevc_transform_add32_8, 3, 4, 12
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TR_ADD_SSE_32_8
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%rep 15
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add r1, 128
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lea r0, [r0+r2*2]
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TR_ADD_SSE_32_8
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%endrep
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RET
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%endif ;ARCH_X86_64
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;-----------------------------------------------------------------------------
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; void ff_hevc_transform_add_10(pixel *dst, int16_t *block, int stride)
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;-----------------------------------------------------------------------------
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%macro TR_ADD_SSE_8_10 4
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mova m0, [%4]
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mova m1, [%4+16]
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mova m2, [%4+32]
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mova m3, [%4+48]
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paddw m0, [%1+0 ]
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paddw m1, [%1+%2 ]
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paddw m2, [%1+%2*2]
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paddw m3, [%1+%3 ]
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CLIPW m0, m4, m5
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CLIPW m1, m4, m5
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CLIPW m2, m4, m5
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CLIPW m3, m4, m5
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mova [%1+0 ], m0
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mova [%1+%2 ], m1
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mova [%1+%2*2], m2
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mova [%1+%3 ], m3
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%endmacro
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%macro TR_ADD_MMX4_10 3
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mova m0, [%1+0 ]
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mova m1, [%1+%2 ]
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paddw m0, [%3]
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paddw m1, [%3+8]
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CLIPW m0, m2, m3
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CLIPW m1, m2, m3
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mova [%1+0 ], m0
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mova [%1+%2 ], m1
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%endmacro
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%macro TRANS_ADD_SSE_16_10 3
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mova m0, [%3]
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mova m1, [%3+16]
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mova m2, [%3+32]
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mova m3, [%3+48]
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paddw m0, [%1 ]
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paddw m1, [%1+16 ]
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paddw m2, [%1+%2 ]
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paddw m3, [%1+%2+16]
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CLIPW m0, m4, m5
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CLIPW m1, m4, m5
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CLIPW m2, m4, m5
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CLIPW m3, m4, m5
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mova [%1 ], m0
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mova [%1+16 ], m1
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mova [%1+%2 ], m2
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mova [%1+%2+16], m3
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%endmacro
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%macro TRANS_ADD_SSE_32_10 2
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mova m0, [%2]
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mova m1, [%2+16]
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mova m2, [%2+32]
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mova m3, [%2+48]
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paddw m0, [%1 ]
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paddw m1, [%1+16]
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paddw m2, [%1+32]
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paddw m3, [%1+48]
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CLIPW m0, m4, m5
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CLIPW m1, m4, m5
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CLIPW m2, m4, m5
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CLIPW m3, m4, m5
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mova [%1 ], m0
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mova [%1+16], m1
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mova [%1+32], m2
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mova [%1+48], m3
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%endmacro
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%macro TRANS_ADD16_AVX2 4
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mova m0, [%4]
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mova m1, [%4+32]
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mova m2, [%4+64]
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mova m3, [%4+96]
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paddw m0, [%1+0 ]
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paddw m1, [%1+%2 ]
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paddw m2, [%1+%2*2]
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paddw m3, [%1+%3 ]
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CLIPW m0, m4, m5
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CLIPW m1, m4, m5
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CLIPW m2, m4, m5
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CLIPW m3, m4, m5
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mova [%1+0 ], m0
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mova [%1+%2 ], m1
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mova [%1+%2*2], m2
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mova [%1+%3 ], m3
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%endmacro
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%macro TRANS_ADD32_AVX2 3
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mova m0, [%3]
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mova m1, [%3+32]
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mova m2, [%3+64]
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mova m3, [%3+96]
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paddw m0, [%1 ]
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paddw m1, [%1+32 ]
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paddw m2, [%1+%2 ]
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paddw m3, [%1+%2+32]
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CLIPW m0, m4, m5
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CLIPW m1, m4, m5
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CLIPW m2, m4, m5
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CLIPW m3, m4, m5
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mova [%1 ], m0
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mova [%1+32 ], m1
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mova [%1+%2 ], m2
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mova [%1+%2+32], m3
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%endmacro
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INIT_MMX mmxext
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cglobal hevc_transform_add4_10,3,4, 6
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pxor m2, m2
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mova m3, [max_pixels_10]
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TR_ADD_MMX4_10 r0, r2, r1
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add r1, 16
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lea r0, [r0+2*r2]
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TR_ADD_MMX4_10 r0, r2, r1
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RET
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;-----------------------------------------------------------------------------
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; void ff_hevc_transform_add_10(pixel *dst, int16_t *block, int stride)
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;-----------------------------------------------------------------------------
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INIT_XMM sse2
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cglobal hevc_transform_add8_10,3,4,6
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pxor m4, m4
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mova m5, [max_pixels_10]
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lea r3, [r2*3]
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TR_ADD_SSE_8_10 r0, r2, r3, r1
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lea r0, [r0+r2*4]
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add r1, 64
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TR_ADD_SSE_8_10 r0, r2, r3, r1
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RET
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cglobal hevc_transform_add16_10,3,4,6
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pxor m4, m4
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mova m5, [max_pixels_10]
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TRANS_ADD_SSE_16_10 r0, r2, r1
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%rep 7
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lea r0, [r0+r2*2]
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add r1, 64
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TRANS_ADD_SSE_16_10 r0, r2, r1
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%endrep
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RET
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cglobal hevc_transform_add32_10,3,4,6
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pxor m4, m4
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mova m5, [max_pixels_10]
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TRANS_ADD_SSE_32_10 r0, r1
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%rep 31
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lea r0, [r0+r2]
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add r1, 64
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TRANS_ADD_SSE_32_10 r0, r1
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%endrep
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RET
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%if HAVE_AVX2_EXTERNAL
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INIT_YMM avx2
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cglobal hevc_transform_add16_10,3,4,6
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pxor m4, m4
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mova m5, [max_pixels_10]
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lea r3, [r2*3]
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TRANS_ADD16_AVX2 r0, r2, r3, r1
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%rep 3
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lea r0, [r0+r2*4]
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add r1, 128
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TRANS_ADD16_AVX2 r0, r2, r3, r1
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%endrep
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RET
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cglobal hevc_transform_add32_10,3,4,6
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pxor m4, m4
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mova m5, [max_pixels_10]
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TRANS_ADD32_AVX2 r0, r2, r1
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%rep 15
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lea r0, [r0+r2*2]
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add r1, 128
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TRANS_ADD32_AVX2 r0, r2, r1
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%endrep
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RET
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%endif ;HAVE_AVX_EXTERNAL
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