97f074f134
Incorporated review comment. Removed "__" from volatile. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com> Reviewed-by: Nedeljko Babic <Nedeljko.Babic@imgtec.com> Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
419 lines
17 KiB
C
419 lines
17 KiB
C
/*
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* Copyright (c) 2015 Manojkumar Bhosale (Manojkumar.Bhosale@imgtec.com)
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef AVUTIL_MIPS_GENERIC_MACROS_MSA_H
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#define AVUTIL_MIPS_GENERIC_MACROS_MSA_H
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#include <stdint.h>
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#include <msa.h>
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#define LOAD_UB(psrc) \
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( { \
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v16u8 out_m; \
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out_m = *((v16u8 *) (psrc)); \
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out_m; \
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} )
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#define LOAD_SB(psrc) \
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( { \
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v16i8 out_m; \
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out_m = *((v16i8 *) (psrc)); \
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out_m; \
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} )
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#define LOAD_SH(psrc) \
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( { \
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v8i16 out_m; \
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out_m = *((v8i16 *) (psrc)); \
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out_m; \
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} )
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#define STORE_SH(vec, pdest) \
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{ \
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*((v8i16 *) (pdest)) = (vec); \
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}
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#define STORE_SW(vec, pdest) \
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{ \
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*((v4i32 *) (pdest)) = (vec); \
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}
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#if (__mips_isa_rev >= 6)
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#define STORE_WORD(pdst, val) \
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{ \
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uint8_t *dst_ptr_m = (uint8_t *) (pdst); \
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uint32_t val_m = (val); \
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\
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__asm__ volatile ( \
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"sw %[val_m], %[dst_ptr_m] \n\t" \
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\
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: [dst_ptr_m] "=m" (*dst_ptr_m) \
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: [val_m] "r" (val_m) \
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); \
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}
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#define STORE_DWORD(pdst, val) \
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{ \
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uint8_t *dst_ptr_m = (uint8_t *) (pdst); \
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uint64_t val_m = (val); \
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\
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__asm__ volatile ( \
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"sd %[val_m], %[dst_ptr_m] \n\t" \
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\
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: [dst_ptr_m] "=m" (*dst_ptr_m) \
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: [val_m] "r" (val_m) \
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); \
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}
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#else
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#define STORE_WORD(pdst, val) \
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{ \
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uint8_t *dst_ptr_m = (uint8_t *) (pdst); \
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uint32_t val_m = (val); \
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\
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__asm__ volatile ( \
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"usw %[val_m], %[dst_ptr_m] \n\t" \
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\
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: [dst_ptr_m] "=m" (*dst_ptr_m) \
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: [val_m] "r" (val_m) \
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); \
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}
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#define STORE_DWORD(pdst, val) \
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{ \
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uint8_t *dst1_m = (uint8_t *) (pdst); \
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uint8_t *dst2_m = ((uint8_t *) (pdst)) + 4; \
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uint32_t val0_m, val1_m; \
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\
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val0_m = (uint32_t) ((val) & 0x00000000FFFFFFFF); \
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val1_m = (uint32_t) (((val) >> 32) & 0x00000000FFFFFFFF); \
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\
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__asm__ volatile ( \
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"usw %[val0_m], %[dst1_m] \n\t" \
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"usw %[val1_m], %[dst2_m] \n\t" \
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\
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: [dst1_m] "=m" (*dst1_m), [dst2_m] "=m" (*dst2_m) \
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: [val0_m] "r" (val0_m), [val1_m] "r" (val1_m) \
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); \
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}
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#endif
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#define LOAD_2VECS_SB(psrc, stride, \
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val0, val1) \
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{ \
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val0 = LOAD_SB(psrc + 0 * stride); \
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val1 = LOAD_SB(psrc + 1 * stride); \
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}
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#define LOAD_4VECS_SB(psrc, stride, \
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val0, val1, val2, val3) \
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{ \
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val0 = LOAD_SB(psrc + 0 * stride); \
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val1 = LOAD_SB(psrc + 1 * stride); \
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val2 = LOAD_SB(psrc + 2 * stride); \
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val3 = LOAD_SB(psrc + 3 * stride); \
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}
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#define LOAD_6VECS_SB(psrc, stride, \
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out0, out1, out2, out3, out4, out5) \
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{ \
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LOAD_4VECS_SB((psrc), (stride), \
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(out0), (out1), (out2), (out3)); \
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LOAD_2VECS_SB((psrc + 4 * stride), (stride), \
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(out4), (out5)); \
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}
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#define LOAD_7VECS_SB(psrc, stride, \
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val0, val1, val2, val3, \
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val4, val5, val6) \
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{ \
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val0 = LOAD_SB((psrc) + 0 * (stride)); \
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val1 = LOAD_SB((psrc) + 1 * (stride)); \
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val2 = LOAD_SB((psrc) + 2 * (stride)); \
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val3 = LOAD_SB((psrc) + 3 * (stride)); \
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val4 = LOAD_SB((psrc) + 4 * (stride)); \
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val5 = LOAD_SB((psrc) + 5 * (stride)); \
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val6 = LOAD_SB((psrc) + 6 * (stride)); \
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}
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#define LOAD_8VECS_SB(psrc, stride, \
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out0, out1, out2, out3, \
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out4, out5, out6, out7) \
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{ \
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LOAD_4VECS_SB((psrc), (stride), \
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(out0), (out1), (out2), (out3)); \
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LOAD_4VECS_SB((psrc + 4 * stride), (stride), \
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(out4), (out5), (out6), (out7)); \
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}
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#define STORE_2VECS_SH(ptr, stride, \
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in0, in1) \
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{ \
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STORE_SH(in0, ((ptr) + 0 * stride)); \
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STORE_SH(in1, ((ptr) + 1 * stride)); \
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}
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#define STORE_4VECS_SH(ptr, stride, \
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in0, in1, in2, in3) \
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{ \
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STORE_SH(in0, ((ptr) + 0 * stride)); \
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STORE_SH(in1, ((ptr) + 1 * stride)); \
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STORE_SH(in2, ((ptr) + 2 * stride)); \
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STORE_SH(in3, ((ptr) + 3 * stride)); \
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}
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#define STORE_6VECS_SH(ptr, stride, \
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in0, in1, in2, in3, \
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in4, in5) \
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{ \
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STORE_SH(in0, ((ptr) + 0 * stride)); \
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STORE_SH(in1, ((ptr) + 1 * stride)); \
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STORE_SH(in2, ((ptr) + 2 * stride)); \
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STORE_SH(in3, ((ptr) + 3 * stride)); \
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STORE_SH(in4, ((ptr) + 4 * stride)); \
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STORE_SH(in5, ((ptr) + 5 * stride)); \
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}
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#define STORE_8VECS_SH(ptr, stride, \
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in0, in1, in2, in3, \
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in4, in5, in6, in7) \
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{ \
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STORE_SH(in0, ((ptr) + 0 * stride)); \
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STORE_SH(in1, ((ptr) + 1 * stride)); \
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STORE_SH(in2, ((ptr) + 2 * stride)); \
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STORE_SH(in3, ((ptr) + 3 * stride)); \
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STORE_SH(in4, ((ptr) + 4 * stride)); \
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STORE_SH(in5, ((ptr) + 5 * stride)); \
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STORE_SH(in6, ((ptr) + 6 * stride)); \
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STORE_SH(in7, ((ptr) + 7 * stride)); \
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}
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#define ILVR_B_2VECS_SB(in0_r, in1_r, in0_l, in1_l, \
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out0, out1) \
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{ \
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out0 = __msa_ilvr_b((v16i8) (in0_l), (v16i8) (in0_r)); \
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out1 = __msa_ilvr_b((v16i8) (in1_l), (v16i8) (in1_r)); \
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}
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#define ILVR_B_4VECS_SB(in0_r, in1_r, in2_r, in3_r, \
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in0_l, in1_l, in2_l, in3_l, \
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out0, out1, out2, out3) \
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{ \
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ILVR_B_2VECS_SB(in0_r, in1_r, in0_l, in1_l, \
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out0, out1); \
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ILVR_B_2VECS_SB(in2_r, in3_r, in2_l, in3_l, \
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out2, out3); \
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}
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#define ILVR_B_6VECS_SB(in0_r, in1_r, in2_r, \
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in3_r, in4_r, in5_r, \
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in0_l, in1_l, in2_l, \
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in3_l, in4_l, in5_l, \
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out0, out1, out2, \
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out3, out4, out5) \
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{ \
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ILVR_B_2VECS_SB(in0_r, in1_r, in0_l, in1_l, \
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out0, out1); \
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ILVR_B_2VECS_SB(in2_r, in3_r, in2_l, in3_l, \
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out2, out3); \
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ILVR_B_2VECS_SB(in4_r, in5_r, in4_l, in5_l, \
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out4, out5); \
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}
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#define ILVR_B_8VECS_SB(in0_r, in1_r, in2_r, in3_r, \
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in4_r, in5_r, in6_r, in7_r, \
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in0_l, in1_l, in2_l, in3_l, \
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in4_l, in5_l, in6_l, in7_l, \
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out0, out1, out2, out3, \
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out4, out5, out6, out7) \
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{ \
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ILVR_B_2VECS_SB(in0_r, in1_r, in0_l, in1_l, \
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out0, out1); \
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ILVR_B_2VECS_SB(in2_r, in3_r, in2_l, in3_l, \
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out2, out3); \
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ILVR_B_2VECS_SB(in4_r, in5_r, in4_l, in5_l, \
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out4, out5); \
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ILVR_B_2VECS_SB(in6_r, in7_r, in6_l, in7_l, \
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out6, out7); \
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}
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#define ILVR_H_2VECS_SH(in0_r, in1_r, in0_l, in1_l, \
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out0, out1) \
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{ \
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out0 = __msa_ilvr_h((v8i16) (in0_l), (v8i16) (in0_r)); \
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out1 = __msa_ilvr_h((v8i16) (in1_l), (v8i16) (in1_r)); \
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}
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#define ILVR_H_6VECS_SH(in0_r, in1_r, in2_r, \
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in3_r, in4_r, in5_r, \
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in0_l, in1_l, in2_l, \
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in3_l, in4_l, in5_l, \
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out0, out1, out2, \
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out3, out4, out5) \
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{ \
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ILVR_H_2VECS_SH(in0_r, in1_r, in0_l, in1_l, \
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out0, out1); \
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ILVR_H_2VECS_SH(in2_r, in3_r, in2_l, in3_l, \
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out2, out3); \
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ILVR_H_2VECS_SH(in4_r, in5_r, in4_l, in5_l, \
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out4, out5); \
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}
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#define ILVL_B_2VECS_SB(in0_r, in1_r, in0_l, in1_l, \
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out0, out1) \
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{ \
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out0 = __msa_ilvl_b((v16i8) (in0_l), (v16i8) (in0_r)); \
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out1 = __msa_ilvl_b((v16i8) (in1_l), (v16i8) (in1_r)); \
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}
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#define ILVL_B_4VECS_SB(in0_r, in1_r, in2_r, in3_r, \
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in0_l, in1_l, in2_l, in3_l, \
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out0, out1, out2, out3) \
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{ \
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ILVL_B_2VECS_SB(in0_r, in1_r, in0_l, in1_l, \
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out0, out1); \
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ILVL_B_2VECS_SB(in2_r, in3_r, in2_l, in3_l, \
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out2, out3); \
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}
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#define ILVL_B_6VECS_SB(in0_r, in1_r, in2_r, \
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in3_r, in4_r, in5_r, \
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in0_l, in1_l, in2_l, \
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in3_l, in4_l, in5_l, \
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out0, out1, out2, \
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out3, out4, out5) \
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{ \
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ILVL_B_2VECS_SB(in0_r, in1_r, in0_l, in1_l, \
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out0, out1); \
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ILVL_B_2VECS_SB(in2_r, in3_r, in2_l, in3_l, \
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out2, out3); \
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ILVL_B_2VECS_SB(in4_r, in5_r, in4_l, in5_l, \
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out4, out5); \
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}
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#define ILVL_H_2VECS_SH(in0_r, in1_r, in0_l, in1_l, \
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out0, out1) \
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{ \
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out0 = __msa_ilvl_h((v8i16) (in0_l), (v8i16) (in0_r)); \
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out1 = __msa_ilvl_h((v8i16) (in1_l), (v8i16) (in1_r)); \
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}
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#define ILVL_H_6VECS_SH(in0_r, in1_r, in2_r, \
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in3_r, in4_r, in5_r, \
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in0_l, in1_l, in2_l, \
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in3_l, in4_l, in5_l, \
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out0, out1, out2, \
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out3, out4, out5) \
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{ \
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ILVL_H_2VECS_SH(in0_r, in1_r, in0_l, in1_l, \
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out0, out1); \
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ILVL_H_2VECS_SH(in2_r, in3_r, in2_l, in3_l, \
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out2, out3); \
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ILVL_H_2VECS_SH(in4_r, in5_r, in4_l, in5_l, \
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out4, out5); \
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}
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#define ILVR_D_2VECS_SB(out0, in0_l, in0_r, \
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out1, in1_l, in1_r) \
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{ \
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out0 = (v16i8) __msa_ilvr_d((v2i64) (in0_l), (v2i64) (in0_r)); \
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out1 = (v16i8) __msa_ilvr_d((v2i64) (in1_l), (v2i64) (in1_r)); \
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}
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#define ILVR_D_3VECS_SB(out0, in0_l, in0_r, \
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out1, in1_l, in1_r, \
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out2, in2_l, in2_r) \
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{ \
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ILVR_D_2VECS_SB(out0, in0_l, in0_r, \
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out1, in1_l, in1_r); \
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out2 = (v16i8) __msa_ilvr_d((v2i64) (in2_l), (v2i64) (in2_r)); \
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}
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#define ILVR_D_4VECS_SB(out0, in0_l, in0_r, \
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out1, in1_l, in1_r, \
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out2, in2_l, in2_r, \
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out3, in3_l, in3_r) \
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{ \
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ILVR_D_2VECS_SB(out0, in0_l, in0_r, \
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out1, in1_l, in1_r); \
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ILVR_D_2VECS_SB(out2, in2_l, in2_r, \
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out3, in3_l, in3_r); \
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}
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#define XORI_B_2VECS_SB(val0, val1, \
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out0, out1, xor_val) \
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{ \
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out0 = (v16i8) __msa_xori_b((v16u8) (val0), (xor_val)); \
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out1 = (v16i8) __msa_xori_b((v16u8) (val1), (xor_val)); \
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}
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#define XORI_B_3VECS_SB(val0, val1, val2, \
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out0, out1, out2, \
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xor_val) \
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{ \
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XORI_B_2VECS_SB(val0, val1, \
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out0, out1, xor_val); \
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out2 = (v16i8) __msa_xori_b((v16u8) (val2), (xor_val)); \
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}
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#define XORI_B_4VECS_SB(val0, val1, val2, val3, \
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out0, out1, out2, out3, \
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xor_val) \
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{ \
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XORI_B_2VECS_SB(val0, val1, \
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out0, out1, xor_val); \
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XORI_B_2VECS_SB(val2, val3, \
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out2, out3, xor_val); \
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}
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#define XORI_B_5VECS_SB(val0, val1, val2, val3, val4, \
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out0, out1, out2, out3, out4, \
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xor_val) \
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{ \
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XORI_B_3VECS_SB(val0, val1, val2, \
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out0, out1, out2, xor_val); \
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XORI_B_2VECS_SB(val3, val4, \
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out3, out4, xor_val); \
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}
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#define XORI_B_7VECS_SB(val0, val1, val2, val3, \
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val4, val5, val6, \
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out0, out1, out2, out3, \
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out4, out5, out6, \
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xor_val) \
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{ \
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XORI_B_4VECS_SB(val0, val1, val2, val3, \
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out0, out1, out2, out3, xor_val); \
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XORI_B_3VECS_SB(val4, val5, val6, \
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out4, out5, out6, xor_val); \
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}
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|
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#define XORI_B_8VECS_SB(val0, val1, val2, val3, \
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val4, val5, val6, val7, \
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out0, out1, out2, out3, \
|
|
out4, out5, out6, out7, xor_val) \
|
|
{ \
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XORI_B_4VECS_SB(val0, val1, val2, val3, \
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out0, out1, out2, out3, xor_val); \
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XORI_B_4VECS_SB(val4, val5, val6, val7, \
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out4, out5, out6, out7, xor_val); \
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}
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|
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#endif /* AVUTIL_MIPS_GENERIC_MACROS_MSA_H */
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