771bab7f57
They were introduced in an earlier commit that introduced use of named arguments. One cause was a typo, a second cause appears to be a bug in x264asm that I work around by not using named arguments.
410 lines
11 KiB
NASM
410 lines
11 KiB
NASM
;******************************************************************************
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;* x86-optimized vertical line scaling functions
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;* Copyright (c) 2011 Ronald S. Bultje <rsbultje@gmail.com>
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;* Kieran Kunhya <kieran@kunhya.com>
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;*
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;* This file is part of Libav.
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;*
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;* Libav is free software; you can redistribute it and/or
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;* modify it under the terms of the GNU Lesser General Public
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;* License as published by the Free Software Foundation; either
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;* version 2.1 of the License, or (at your option) any later version.
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;*
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;* Libav is distributed in the hope that it will be useful,
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;* but WITHOUT ANY WARRANTY; without even the implied warranty of
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;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;* Lesser General Public License for more details.
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;*
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;* You should have received a copy of the GNU Lesser General Public
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;* License along with Libav; if not, write to the Free Software
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;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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;******************************************************************************
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%include "x86inc.asm"
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%include "x86util.asm"
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SECTION_RODATA
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minshort: times 8 dw 0x8000
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yuv2yuvX_16_start: times 4 dd 0x4000 - 0x40000000
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yuv2yuvX_10_start: times 4 dd 0x10000
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yuv2yuvX_9_start: times 4 dd 0x20000
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yuv2yuvX_10_upper: times 8 dw 0x3ff
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yuv2yuvX_9_upper: times 8 dw 0x1ff
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pd_4: times 4 dd 4
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pd_4min0x40000:times 4 dd 4 - (0x40000)
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pw_16: times 8 dw 16
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pw_32: times 8 dw 32
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pw_512: times 8 dw 512
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pw_1024: times 8 dw 1024
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SECTION .text
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;-----------------------------------------------------------------------------
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; vertical line scaling
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;
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; void yuv2plane1_<output_size>_<opt>(const int16_t *src, uint8_t *dst, int dstW,
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; const uint8_t *dither, int offset)
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; and
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; void yuv2planeX_<output_size>_<opt>(const int16_t *filter, int filterSize,
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; const int16_t **src, uint8_t *dst, int dstW,
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; const uint8_t *dither, int offset)
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;
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; Scale one or $filterSize lines of source data to generate one line of output
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; data. The input is 15-bit in int16_t if $output_size is [8,10] and 19-bit in
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; int32_t if $output_size is 16. $filter is 12-bits. $filterSize is a multiple
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; of 2. $offset is either 0 or 3. $dither holds 8 values.
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;-----------------------------------------------------------------------------
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%macro yuv2planeX_fn 3
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%if ARCH_X86_32
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%define cntr_reg fltsizeq
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%define movsx mov
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%else
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%define cntr_reg r11
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%define movsx movsxd
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%endif
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cglobal yuv2planeX_%1, %3, 7, %2, filter, fltsize, src, dst, w, dither, offset
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%if %1 == 8 || %1 == 9 || %1 == 10
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pxor m6, m6
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%endif ; %1 == 8/9/10
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%if %1 == 8
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%if ARCH_X86_32
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%assign pad 0x2c - (stack_offset & 15)
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SUB rsp, pad
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%define m_dith m7
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%else ; x86-64
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%define m_dith m9
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%endif ; x86-32
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; create registers holding dither
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movq m_dith, [ditherq] ; dither
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test offsetd, offsetd
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jz .no_rot
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%if mmsize == 16
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punpcklqdq m_dith, m_dith
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%endif ; mmsize == 16
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PALIGNR m_dith, m_dith, 3, m0
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.no_rot:
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%if mmsize == 16
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punpcklbw m_dith, m6
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%if ARCH_X86_64
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punpcklwd m8, m_dith, m6
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pslld m8, 12
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%else ; x86-32
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punpcklwd m5, m_dith, m6
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pslld m5, 12
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%endif ; x86-32/64
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punpckhwd m_dith, m6
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pslld m_dith, 12
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%if ARCH_X86_32
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mova [rsp+ 0], m5
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mova [rsp+16], m_dith
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%endif
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%else ; mmsize == 8
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punpcklbw m5, m_dith, m6
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punpckhbw m_dith, m6
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punpcklwd m4, m5, m6
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punpckhwd m5, m6
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punpcklwd m3, m_dith, m6
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punpckhwd m_dith, m6
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pslld m4, 12
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pslld m5, 12
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pslld m3, 12
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pslld m_dith, 12
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mova [rsp+ 0], m4
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mova [rsp+ 8], m5
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mova [rsp+16], m3
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mova [rsp+24], m_dith
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%endif ; mmsize == 8/16
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%endif ; %1 == 8
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xor r5, r5
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.pixelloop:
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%assign %%i 0
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; the rep here is for the 8bit output mmx case, where dither covers
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; 8 pixels but we can only handle 2 pixels per register, and thus 4
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; pixels per iteration. In order to not have to keep track of where
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; we are w.r.t. dithering, we unroll the mmx/8bit loop x2.
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%if %1 == 8
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%rep 16/mmsize
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%endif ; %1 == 8
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%if %1 == 8
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%if ARCH_X86_32
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mova m2, [rsp+mmsize*(0+%%i)]
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mova m1, [rsp+mmsize*(1+%%i)]
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%else ; x86-64
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mova m2, m8
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mova m1, m_dith
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%endif ; x86-32/64
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%else ; %1 == 9/10/16
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mova m1, [yuv2yuvX_%1_start]
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mova m2, m1
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%endif ; %1 == 8/9/10/16
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movsx cntr_reg, r1m ; FIXME should be fltsizem, but the assembler does the wrong thing b/c of SUB above
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.filterloop_ %+ %%i:
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; input pixels
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mov r6, [srcq+gprsize*cntr_reg-2*gprsize]
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%if %1 == 16
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mova m3, [r6+r5*4]
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mova m5, [r6+r5*4+mmsize]
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%else ; %1 == 8/9/10
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mova m3, [r6+r5*2]
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%endif ; %1 == 8/9/10/16
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mov r6, [srcq+gprsize*cntr_reg-gprsize]
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%if %1 == 16
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mova m4, [r6+r5*4]
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mova m6, [r6+r5*4+mmsize]
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%else ; %1 == 8/9/10
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mova m4, [r6+r5*2]
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%endif ; %1 == 8/9/10/16
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; coefficients
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movd m0, [filterq+2*cntr_reg-4] ; coeff[0], coeff[1]
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%if %1 == 16
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pshuflw m7, m0, 0 ; coeff[0]
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pshuflw m0, m0, 0x55 ; coeff[1]
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pmovsxwd m7, m7 ; word -> dword
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pmovsxwd m0, m0 ; word -> dword
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pmulld m3, m7
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pmulld m5, m7
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pmulld m4, m0
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pmulld m6, m0
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paddd m2, m3
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paddd m1, m5
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paddd m2, m4
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paddd m1, m6
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%else ; %1 == 10/9/8
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punpcklwd m5, m3, m4
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punpckhwd m3, m4
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SPLATD m0, m0
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pmaddwd m5, m0
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pmaddwd m3, m0
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paddd m2, m5
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paddd m1, m3
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%endif ; %1 == 8/9/10/16
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sub cntr_reg, 2
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jg .filterloop_ %+ %%i
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%if %1 == 16
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psrad m2, 31 - %1
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psrad m1, 31 - %1
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%else ; %1 == 10/9/8
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psrad m2, 27 - %1
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psrad m1, 27 - %1
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%endif ; %1 == 8/9/10/16
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%if %1 == 8
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packssdw m2, m1
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packuswb m2, m2
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movh [dstq+r5*1], m2
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%else ; %1 == 9/10/16
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%if %1 == 16
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packssdw m2, m1
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paddw m2, [minshort]
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%else ; %1 == 9/10
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%if cpuflag(sse4)
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packusdw m2, m1
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%else ; mmx2/sse2
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packssdw m2, m1
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pmaxsw m2, m6
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%endif ; mmx2/sse2/sse4/avx
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pminsw m2, [yuv2yuvX_%1_upper]
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%endif ; %1 == 9/10/16
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mova [dstq+r5*2], m2
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%endif ; %1 == 8/9/10/16
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add r5, mmsize/2
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sub wd, mmsize/2
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%if %1 == 8
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%assign %%i %%i+2
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%endrep
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%endif ; %1 == 8
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jg .pixelloop
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%if %1 == 8
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%if ARCH_X86_32
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ADD rsp, pad
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RET
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%else ; x86-64
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REP_RET
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%endif ; x86-32/64
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%else ; %1 == 9/10/16
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REP_RET
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%endif ; %1 == 8/9/10/16
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%endmacro
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%define PALIGNR PALIGNR_MMX
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%if ARCH_X86_32
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INIT_MMX mmx2
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yuv2planeX_fn 8, 0, 7
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yuv2planeX_fn 9, 0, 5
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yuv2planeX_fn 10, 0, 5
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%endif
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INIT_XMM sse2
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yuv2planeX_fn 8, 10, 7
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yuv2planeX_fn 9, 7, 5
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yuv2planeX_fn 10, 7, 5
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%define PALIGNR PALIGNR_SSSE3
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INIT_XMM sse4
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yuv2planeX_fn 8, 10, 7
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yuv2planeX_fn 9, 7, 5
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yuv2planeX_fn 10, 7, 5
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yuv2planeX_fn 16, 8, 5
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INIT_XMM avx
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yuv2planeX_fn 8, 10, 7
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yuv2planeX_fn 9, 7, 5
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yuv2planeX_fn 10, 7, 5
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; %1=outout-bpc, %2=alignment (u/a)
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%macro yuv2plane1_mainloop 2
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.loop_%2:
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%if %1 == 8
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paddsw m0, m2, [srcq+wq*2+mmsize*0]
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paddsw m1, m3, [srcq+wq*2+mmsize*1]
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psraw m0, 7
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psraw m1, 7
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packuswb m0, m1
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mov%2 [dstq+wq], m0
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%elif %1 == 16
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paddd m0, m4, [srcq+wq*4+mmsize*0]
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paddd m1, m4, [srcq+wq*4+mmsize*1]
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paddd m2, m4, [srcq+wq*4+mmsize*2]
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paddd m3, m4, [srcq+wq*4+mmsize*3]
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psrad m0, 3
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psrad m1, 3
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psrad m2, 3
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psrad m3, 3
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%if cpuflag(sse4) ; avx/sse4
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packusdw m0, m1
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packusdw m2, m3
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%else ; mmx/sse2
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packssdw m0, m1
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packssdw m2, m3
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paddw m0, m5
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paddw m2, m5
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%endif ; mmx/sse2/sse4/avx
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mov%2 [dstq+wq*2+mmsize*0], m0
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mov%2 [dstq+wq*2+mmsize*1], m2
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%else ; %1 == 9/10
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paddsw m0, m2, [srcq+wq*2+mmsize*0]
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paddsw m1, m2, [srcq+wq*2+mmsize*1]
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psraw m0, 15 - %1
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psraw m1, 15 - %1
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pmaxsw m0, m4
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pmaxsw m1, m4
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pminsw m0, m3
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pminsw m1, m3
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mov%2 [dstq+wq*2+mmsize*0], m0
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mov%2 [dstq+wq*2+mmsize*1], m1
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%endif
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add wq, mmsize
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jl .loop_%2
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%endmacro
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%macro yuv2plane1_fn 3
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cglobal yuv2plane1_%1, %3, %3, %2, src, dst, w, dither, offset
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movsxdifnidn wq, wd
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add wq, mmsize - 1
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and wq, ~(mmsize - 1)
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%if %1 == 8
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add dstq, wq
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%else ; %1 != 8
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lea dstq, [dstq+wq*2]
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%endif ; %1 == 8
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%if %1 == 16
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lea srcq, [srcq+wq*4]
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%else ; %1 != 16
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lea srcq, [srcq+wq*2]
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%endif ; %1 == 16
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neg wq
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%if %1 == 8
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pxor m4, m4 ; zero
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; create registers holding dither
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movq m3, [ditherq] ; dither
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test offsetd, offsetd
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jz .no_rot
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%if mmsize == 16
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punpcklqdq m3, m3
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%endif ; mmsize == 16
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PALIGNR_MMX m3, m3, 3, m2
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.no_rot:
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%if mmsize == 8
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mova m2, m3
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punpckhbw m3, m4 ; byte->word
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punpcklbw m2, m4 ; byte->word
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%else
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punpcklbw m3, m4
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mova m2, m3
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%endif
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%elif %1 == 9
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pxor m4, m4
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mova m3, [pw_512]
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mova m2, [pw_32]
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%elif %1 == 10
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pxor m4, m4
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mova m3, [pw_1024]
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mova m2, [pw_16]
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%else ; %1 == 16
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%if cpuflag(sse4) ; sse4/avx
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mova m4, [pd_4]
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%else ; mmx/sse2
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mova m4, [pd_4min0x40000]
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mova m5, [minshort]
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%endif ; mmx/sse2/sse4/avx
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%endif ; %1 == ..
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; actual pixel scaling
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%if mmsize == 8
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yuv2plane1_mainloop %1, a
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%else ; mmsize == 16
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test dstq, 15
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jnz .unaligned
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yuv2plane1_mainloop %1, a
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REP_RET
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.unaligned:
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yuv2plane1_mainloop %1, u
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%endif ; mmsize == 8/16
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REP_RET
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%endmacro
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%if ARCH_X86_32
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INIT_MMX mmx
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yuv2plane1_fn 8, 0, 5
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yuv2plane1_fn 16, 0, 3
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INIT_MMX mmx2
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yuv2plane1_fn 9, 0, 3
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yuv2plane1_fn 10, 0, 3
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%endif
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INIT_XMM sse2
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yuv2plane1_fn 8, 5, 5
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yuv2plane1_fn 9, 5, 3
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yuv2plane1_fn 10, 5, 3
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yuv2plane1_fn 16, 6, 3
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INIT_XMM sse4
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yuv2plane1_fn 16, 5, 3
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INIT_XMM avx
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yuv2plane1_fn 8, 5, 5
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yuv2plane1_fn 9, 5, 3
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yuv2plane1_fn 10, 5, 3
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yuv2plane1_fn 16, 5, 3
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