81dc6a2a3c
Signed-off-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Janne Grunau <janne-libav@jannau.net>
139 lines
5.6 KiB
ArmAsm
139 lines
5.6 KiB
ArmAsm
/*
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* Copyright (c) 2011 Janne Grunau <janne-libav@jannau.net>
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*
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* This file is part of Libav.
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*
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* Libav is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* Libav is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with Libav; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "asm.S"
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.macro rv34_inv_transform
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mov r1, #16
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vld1.16 {d28}, [r0,:64], r1 @ block[i+8*0]
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vld1.16 {d29}, [r0,:64], r1 @ block[i+8*1]
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vld1.16 {d30}, [r0,:64], r1 @ block[i+8*2]
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vld1.16 {d31}, [r0,:64], r1 @ block[i+8*3]
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vmov.s16 d0, #13
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vshll.s16 q12, d29, #3
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vshll.s16 q13, d29, #4
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vshll.s16 q9, d31, #3
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vshll.s16 q1, d31, #4
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vmull.s16 q10, d28, d0
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vmlal.s16 q10, d30, d0
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vmull.s16 q11, d28, d0
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vmlsl.s16 q11, d30, d0
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vsubw.s16 q12, q12, d29 @ z2 = block[i+8*1]*7
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vaddw.s16 q13, q13, d29 @ z3 = block[i+8*1]*17
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vsubw.s16 q9, q9, d31
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vaddw.s16 q1, q1, d31
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vadd.s32 q13, q13, q9 @ z3 = 17*block[i+8*1] + 7*block[i+8*3]
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vsub.s32 q12, q12, q1 @ z2 = 7*block[i+8*1] - 17*block[i+8*3]
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vadd.s32 q1, q10, q13 @ z0 + z3
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vadd.s32 q2, q11, q12 @ z1 + z2
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vsub.s32 q8, q10, q13 @ z0 - z3
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vsub.s32 q3, q11, q12 @ z1 - z2
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vtrn.32 q1, q2
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vtrn.32 q3, q8
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vswp d3, d6
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vswp d5, d16
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vmov.s32 d0, #13
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vadd.s32 q10, q1, q3
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vsub.s32 q11, q1, q3
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vshl.s32 q12, q2, #3
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vshl.s32 q9, q2, #4
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vmul.s32 q13, q11, d0[0]
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vshl.s32 q11, q8, #4
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vadd.s32 q9, q9, q2
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vshl.s32 q15, q8, #3
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vsub.s32 q12, q12, q2
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vadd.s32 q11, q11, q8
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vmul.s32 q14, q10, d0[0]
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vsub.s32 q8, q15, q8
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vsub.s32 q12, q12, q11
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vadd.s32 q9, q9, q8
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vadd.s32 q2, q13, q12 @ z1 + z2
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vadd.s32 q1, q14, q9 @ z0 + z3
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vsub.s32 q3, q13, q12 @ z1 - z2
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vsub.s32 q15, q14, q9 @ z0 - z3
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.endm
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/* void ff_rv34_inv_transform_neon(DCTELEM *block); */
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function ff_rv34_inv_transform_neon, export=1
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mov r2, r0
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rv34_inv_transform
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vrshrn.s32 d1, q2, #10 @ (z1 + z2) >> 10
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vrshrn.s32 d0, q1, #10 @ (z0 + z3) >> 10
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vrshrn.s32 d2, q3, #10 @ (z1 - z2) >> 10
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vrshrn.s32 d3, q15, #10 @ (z0 - z3) >> 10
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vst4.16 {d0[0], d1[0], d2[0], d3[0]}, [r2,:64], r1
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vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r2,:64], r1
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vst4.16 {d0[2], d1[2], d2[2], d3[2]}, [r2,:64], r1
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vst4.16 {d0[3], d1[3], d2[3], d3[3]}, [r2,:64], r1
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bx lr
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endfunc
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/* void rv34_inv_transform_noround_neon(DCTELEM *block); */
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function ff_rv34_inv_transform_noround_neon, export=1
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mov r2, r0
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rv34_inv_transform
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vshl.s32 q11, q2, #1
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vshl.s32 q10, q1, #1
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vshl.s32 q12, q3, #1
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vshl.s32 q13, q15, #1
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vadd.s32 q11, q11, q2
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vadd.s32 q10, q10, q1
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vadd.s32 q12, q12, q3
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vadd.s32 q13, q13, q15
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vshrn.s32 d0, q10, #11 @ (z0 + z3)*3 >> 11
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vshrn.s32 d1, q11, #11 @ (z1 + z2)*3 >> 11
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vshrn.s32 d2, q12, #11 @ (z1 - z2)*3 >> 11
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vshrn.s32 d3, q13, #11 @ (z0 - z3)*3 >> 11
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vst4.16 {d0[0], d1[0], d2[0], d3[0]}, [r2,:64], r1
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vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r2,:64], r1
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vst4.16 {d0[2], d1[2], d2[2], d3[2]}, [r2,:64], r1
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vst4.16 {d0[3], d1[3], d2[3], d3[3]}, [r2,:64], r1
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bx lr
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endfunc
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/* void rv34_inv_transform_dc_c(DCTELEM *block) */
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function ff_rv34_inv_transform_dc_neon, export=1
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vld1.16 {d28[]}, [r0,:16] @ block[0]
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vmov.i16 d4, #169
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mov r1, #16
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vmull.s16 q3, d28, d4
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vrshrn.s32 d0, q3, #10
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vst1.16 {d0}, [r0,:64], r1
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vst1.16 {d0}, [r0,:64], r1
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vst1.16 {d0}, [r0,:64], r1
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vst1.16 {d0}, [r0,:64], r1
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bx lr
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endfunc
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/* void rv34_inv_transform_dc_noround_c(DCTELEM *block) */
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function ff_rv34_inv_transform_noround_dc_neon, export=1
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vld1.16 {d28[]}, [r0,:16] @ block[0]
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vmov.i16 d4, #251
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vorr.s16 d4, #256 @ 13^2 * 3
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mov r1, #16
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vmull.s16 q3, d28, d4
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vshrn.s32 d0, q3, #11
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vst1.64 {d0}, [r0,:64], r1
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vst1.64 {d0}, [r0,:64], r1
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vst1.64 {d0}, [r0,:64], r1
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vst1.64 {d0}, [r0,:64], r1
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bx lr
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endfunc
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