5dc7363446
Adaption to swr by: Michael Niedermayer <michaelni@gmx.at> Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
131 lines
4.9 KiB
ArmAsm
131 lines
4.9 KiB
ArmAsm
/*
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* Copyright (c) 2008 Mans Rullgard <mans@mansr.com>
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*
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* This file is part of libswresample.
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*
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* libswresample is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* libswresample is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with libswresample; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "config.h"
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#include "libavutil/arm/asm.S"
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function swri_oldapi_conv_flt_to_s16_neon, export=1
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subs r2, r2, #8
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vld1.32 {q0}, [r1,:128]!
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vcvt.s32.f32 q8, q0, #31
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vld1.32 {q1}, [r1,:128]!
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vcvt.s32.f32 q9, q1, #31
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beq 3f
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bics r12, r2, #15
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beq 2f
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1: subs r12, r12, #16
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vqrshrn.s32 d4, q8, #16
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vld1.32 {q0}, [r1,:128]!
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vcvt.s32.f32 q0, q0, #31
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vqrshrn.s32 d5, q9, #16
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vld1.32 {q1}, [r1,:128]!
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vcvt.s32.f32 q1, q1, #31
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vqrshrn.s32 d6, q0, #16
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vst1.16 {q2}, [r0,:128]!
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vqrshrn.s32 d7, q1, #16
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vld1.32 {q8}, [r1,:128]!
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vcvt.s32.f32 q8, q8, #31
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vld1.32 {q9}, [r1,:128]!
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vcvt.s32.f32 q9, q9, #31
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vst1.16 {q3}, [r0,:128]!
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bne 1b
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ands r2, r2, #15
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beq 3f
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2: vld1.32 {q0}, [r1,:128]!
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vqrshrn.s32 d4, q8, #16
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vcvt.s32.f32 q0, q0, #31
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vld1.32 {q1}, [r1,:128]!
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vqrshrn.s32 d5, q9, #16
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vcvt.s32.f32 q1, q1, #31
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vqrshrn.s32 d6, q0, #16
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vst1.16 {q2}, [r0,:128]!
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vqrshrn.s32 d7, q1, #16
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vst1.16 {q3}, [r0,:128]!
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bx lr
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3: vqrshrn.s32 d4, q8, #16
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vqrshrn.s32 d5, q9, #16
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vst1.16 {q2}, [r0,:128]!
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bx lr
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endfunc
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function swri_oldapi_conv_fltp_to_s16_2ch_neon, export=1
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ldm r1, {r1, r3}
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subs r2, r2, #8
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vld1.32 {q0}, [r1,:128]!
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vcvt.s32.f32 q8, q0, #31
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vld1.32 {q1}, [r1,:128]!
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vcvt.s32.f32 q9, q1, #31
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vld1.32 {q10}, [r3,:128]!
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vcvt.s32.f32 q10, q10, #31
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vld1.32 {q11}, [r3,:128]!
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vcvt.s32.f32 q11, q11, #31
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beq 3f
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bics r12, r2, #15
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beq 2f
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1: subs r12, r12, #16
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vld1.32 {q0}, [r1,:128]!
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vcvt.s32.f32 q0, q0, #31
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vsri.32 q10, q8, #16
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vld1.32 {q1}, [r1,:128]!
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vcvt.s32.f32 q1, q1, #31
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vld1.32 {q12}, [r3,:128]!
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vcvt.s32.f32 q12, q12, #31
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vld1.32 {q13}, [r3,:128]!
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vsri.32 q11, q9, #16
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vst1.16 {q10}, [r0,:128]!
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vcvt.s32.f32 q13, q13, #31
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vst1.16 {q11}, [r0,:128]!
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vsri.32 q12, q0, #16
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vld1.32 {q8}, [r1,:128]!
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vsri.32 q13, q1, #16
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vst1.16 {q12}, [r0,:128]!
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vcvt.s32.f32 q8, q8, #31
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vld1.32 {q9}, [r1,:128]!
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vcvt.s32.f32 q9, q9, #31
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vld1.32 {q10}, [r3,:128]!
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vcvt.s32.f32 q10, q10, #31
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vld1.32 {q11}, [r3,:128]!
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vcvt.s32.f32 q11, q11, #31
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vst1.16 {q13}, [r0,:128]!
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bne 1b
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ands r2, r2, #15
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beq 3f
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2: vsri.32 q10, q8, #16
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vld1.32 {q0}, [r1,:128]!
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vcvt.s32.f32 q0, q0, #31
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vld1.32 {q1}, [r1,:128]!
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vcvt.s32.f32 q1, q1, #31
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vld1.32 {q12}, [r3,:128]!
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vcvt.s32.f32 q12, q12, #31
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vsri.32 q11, q9, #16
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vld1.32 {q13}, [r3,:128]!
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vcvt.s32.f32 q13, q13, #31
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vst1.16 {q10}, [r0,:128]!
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vsri.32 q12, q0, #16
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vst1.16 {q11}, [r0,:128]!
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vsri.32 q13, q1, #16
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vst1.16 {q12-q13},[r0,:128]!
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bx lr
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3: vsri.32 q10, q8, #16
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vsri.32 q11, q9, #16
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vst1.16 {q10-q11},[r0,:128]!
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bx lr
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endfunc
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