Commit Graph

29 Commits

Author SHA1 Message Date
Michael Niedermayer
4104eb44e6 Merge commit '55519926ef855c671d084ccc151056de9e3d3a77'
* commit '55519926ef855c671d084ccc151056de9e3d3a77':
  x86: Make function prototype comments in assembly code consistent

Conflicts:
	libavcodec/x86/sbrdsp.asm

Merged-by: Michael Niedermayer <michaelni@gmx.at>
2014-03-14 00:01:30 +01:00
Diego Biurrun
55519926ef x86: Make function prototype comments in assembly code consistent
This helps grepping for functions, among other things.
2014-03-13 05:50:29 -07:00
Thilo Borgmann
d814a839ac Reinstate proper FFmpeg license for all files. 2013-08-30 15:47:38 +00:00
Michael Niedermayer
5e1278c640 Merge commit '2c299d4165cd9653153e12270971c2368551b79e'
* commit '2c299d4165cd9653153e12270971c2368551b79e':
  x86: sbrdsp: implement SSE2 qmf_pre_shuffle

Conflicts:
	libavcodec/x86/sbrdsp.asm
	libavcodec/x86/sbrdsp_init.c

Merged-by: Michael Niedermayer <michaelni@gmx.at>
2013-05-10 23:16:09 +02:00
Christophe Gisquet
2c299d4165 x86: sbrdsp: implement SSE2 qmf_pre_shuffle
From 253 to 51 cycles on Arrandale and Win64.
44 cycles on SandyBridge.

Signed-off-by: Anton Khirnov <anton@khirnov.net>
2013-05-10 09:31:27 +02:00
Christophe Gisquet
fc37cd4333 x86: sbrdsp: force PIC addressing for Win64
MSVC complains about the 32bits addressing, while mingw/gcc does not.

Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
2013-05-08 03:07:03 +02:00
Michael Niedermayer
711c8ee71d Merge commit '4a7af92cc80ced8498626401ed21f25ffe6740c8'
* commit '4a7af92cc80ced8498626401ed21f25ffe6740c8':
  sbrdsp: Unroll and use integer operations
  sbrdsp: Unroll sbr_autocorrelate_c
  x86: sbrdsp: Implement SSE2 qmf_deint_bfly

Conflicts:
	libavcodec/sbrdsp.c
	libavcodec/x86/sbrdsp.asm
	libavcodec/x86/sbrdsp_init.c

Merged-by: Michael Niedermayer <michaelni@gmx.at>
2013-05-04 10:07:43 +02:00
Christophe Gisquet
5a97469a4f x86: sbrdsp: Implement SSE2 qmf_deint_bfly
Sandybridge: 47 cycles

Having a loop counter is a 7 cycle gain.
Unrolling is another 7 cycle gain.
Working in reverse scan is another 6 cycles.

Signed-off-by: Diego Biurrun <diego@biurrun.de>
2013-05-03 18:23:14 +02:00
Michael Niedermayer
fc69033371 avcodec/x86/sbrdsp_init: disable using the noise code in x86_64 MSVC, Try #2
This should fix building with MSVC until someone can change the
    code so it works with MSVC

Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
2013-04-24 02:02:25 +02:00
Christophe Gisquet
76c7277385 x86: sbrdsp: implement SSE2 hf_apply_noise
233 to 105 cycles on Arrandale and Win64.
Replacing the multiplication by s_m[m] by a pand and a pxor with
appropriate vectors is slower. Unrolling is a 15 cycles win.
A SSE version was 4 cycles slower.

Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
2013-04-19 13:19:45 +02:00
Christophe Gisquet
2383068cbf x86: sbrdsp: implement SSE2 qmf_pre_shuffle
From 253 to 51 cycles on Arrandale and Win64.
44 cycles on SandyBridge.

Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
2013-04-10 02:42:22 +02:00
Christophe Gisquet
e2946e5c34 x86: sbrdsp: implement SSE qmf_deint_bfly
From 312 to 89/68 (sse/sse2) cycles on Arrandale and Win64.
Sandybridge: 68/47 cycles.

Having a loop counter is a 7 cycle gain.
Unrolling is another 7 cycle gain.
Working in reverse scan is another 6 cycles.

Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
2013-04-08 02:26:34 +02:00
Michael Niedermayer
32bac65ba0 Merge remote-tracking branch 'qatar/master'
* qatar/master:
  x86: sbrdsp: Implement SSE neg_odd_64

Conflicts:
	libavcodec/x86/sbrdsp.asm

Merged-by: Michael Niedermayer <michaelni@gmx.at>
2013-04-06 13:30:19 +02:00
Christophe Gisquet
f4b0d12f5b x86: sbrdsp: Implement SSE neg_odd_64
Timing on Arrandale:
        C   SSE
Win32:  57   44
Win64:  47   38
Unrolling and not storing mask both save some cycles.

Signed-off-by: Diego Biurrun <diego@biurrun.de>
2013-04-05 22:47:04 +02:00
Christophe Gisquet
37a9708391 x86: sbrdsp: implement SSE neg_odd_64
Timing on Arrandale:
        C   SSE
Win32:  57   44
Win64:  47   38
Unrolling and not storing mask both save some cycles.

Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
2013-04-05 16:42:12 +02:00
Michael Niedermayer
c526a01c91 Merge commit '4f50646697606df39317b93c2a427603b77636ee'
* commit '4f50646697606df39317b93c2a427603b77636ee':
  x86: sbrdsp: Implement SSE qmf_post_shuffle

Merged-by: Michael Niedermayer <michaelni@gmx.at>
2013-01-07 01:51:10 +01:00
Michael Niedermayer
8429320313 Merge commit '44a0036d10579ed91e48df24859e54b08a582742'
* commit '44a0036d10579ed91e48df24859e54b08a582742':
  x86: sbrdsp: Implement SSE sum64x5

Merged-by: Michael Niedermayer <michaelni@gmx.at>
2013-01-07 01:40:05 +01:00
Christophe Gisquet
4f50646697 x86: sbrdsp: Implement SSE qmf_post_shuffle
255 to 174 cycles on Arrandale / Win64. Unrolling yields no gain.

Signed-off-by: Diego Biurrun <diego@biurrun.de>
2013-01-06 13:57:01 +01:00
Christophe Gisquet
44a0036d10 x86: sbrdsp: Implement SSE sum64x5
698 to 174 cycles on Arrandale. Unrolling is a 6 cycles gain.

Signed-off-by: Diego Biurrun <diego@biurrun.de>
2013-01-06 13:57:01 +01:00
Michael Niedermayer
0110108a7c sbr_hf_gen_sse: Optimize code a bit more.
Core I7 (Sandy Bridge) 135 to 107 cycles
Core i5 (Arrandale) 162 to 142 (Thanks to Christophe Gisquet for testing)

Reviewed-by: Christophe Gisquet <christophe.gisquet@gmail.com>
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
2012-12-08 17:30:11 +01:00
Christophe Gisquet
2aef3d66c9 SBR DSP x86: implement SSE sbr_hf_gen
Start and end index are multiple of 2, therefore guaranteeing aligned access.
Also, this allows to generate 4 floats per loop, keeping the alignment all
along.

Timing:
- 32 bits: 326c -> 172c
- 64 bits: 323c -> 156c

Signed-off-by: Diego Biurrun <diego@biurrun.de>
2012-12-07 11:04:26 +01:00
Diego Biurrun
04581c8c77 x86: yasm: Use complete source path for macro helper %includes
This is more consistent with the way we handle C #includes and
it simplifies the build system.
2012-10-31 00:37:42 +01:00
Diego Biurrun
6860b4081d x86: include x86inc.asm in x86util.asm
This is necessary to allow refactoring some x86util macros with cpuflags.
2012-10-31 00:37:42 +01:00
Christophe GISQUET
6b81da2fd0 dsputil x86: use SSE float instruction instead of SSE2 integer equivalent
All the more required since the users are pure SSE functions.

Signed-off-by: Ronald S. Bultje <rsbultje@gmail.com>
2012-04-04 11:24:27 -07:00
Ronald S. Bultje
71ea26811c aacsbr: handle m_max values smaller than 4.
Prevents a signflip in the counter, and a subsequent crash because of
overreads/overwrites.

Found-by: Mateusz "j00ru" Jurczyk and Gynvael Coldwind
CC: libav-stable@libav.org
2012-03-23 12:56:08 -07:00
Reimar Döffinger
6eda85e15b sbrdsp.asm: convert all instructions to float/SSE ones.
Since the values are floats, using the float operations
makes sense, improves performance on some CPUs and
makes the code SSE compatible instead of needing SSE2.

Based on suggestion by Jason.

Signed-off-by: Reimar Döffinger <Reimar.Doeffinger@gmx.de>
Signed-off-by: Ronald S. Bultje <rsbultje@gmail.com>
2012-03-07 13:50:13 -08:00
Reimar Döffinger
b5161908e0 SBR DSP: fix SSE code to not use SSE2 instructions.
movq from SSE register _to_ memory is an SSE2 instruction.
Use the SSE movlps function instead that does the same thing.

Signed-off-by: Reimar Döffinger <Reimar.Doeffinger@gmx.de>
Signed-off-by: Ronald S. Bultje <rsbultje@gmail.com>
2012-03-06 13:40:35 -08:00
Christophe GISQUET
2784d18791 SBR DSP x86: implement SSE sbr_hf_g_filt
Unrolling the main loop to process, instead of 4 elements:
- 8: minor gain of 2 cycles (not worth the extra object size)
- 2: loss of 8 cycles.

Assigning STEP to a register is a loss. Output address (Y) is almost always
unaligned.

Timings:
- C (32/64 bits): 117/109 cycles
- SSE: 57 cycles

Signed-off-by: Ronald S. Bultje <rsbultje@gmail.com>
2012-02-23 15:50:09 -08:00
Christophe GISQUET
34454c761f SBR DSP x86: implement SSE sbr_sum_square_sse
The 32bits targets have been compiled with -mfpmath=sse for proper reference.
sbr_sum_square C  /32bits: 82c (unrolled)/102c
               C  /64bits: 69c (unrolled)/82c
               SSE/32bits: 42c
               SSE/64bits: 31c

Use of SSE4.1 dpps to perform the final sum is slower.
Not unrolling to perform 8 operations in a loop yields 10 more cycles.

Signed-off-by: Ronald S. Bultje <rsbultje@gmail.com>
2012-02-23 15:50:06 -08:00