Merge commit 'ba6836c966debc56314ce2ef133c7f0c1fdfdeac'
* commit 'ba6836c966debc56314ce2ef133c7f0c1fdfdeac': arm: Add VFP-accelerated version of dca_lfe_fir Merged-by: Michael Niedermayer <michaelni@gmx.at>
This commit is contained in:
Michael Niedermayer
commit
bacba8e5d1
@ -52,7 +52,8 @@ ARMV6-OBJS-$(CONFIG_VP8_DECODER) += arm/vp8_armv6.o \
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arm/vp8dsp_init_armv6.o \
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arm/vp8dsp_armv6.o
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VFP-OBJS-$(CONFIG_DCA_DECODER) += arm/synth_filter_vfp.o
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VFP-OBJS-$(CONFIG_DCA_DECODER) += arm/dcadsp_vfp.o \
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arm/synth_filter_vfp.o
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VFP-OBJS-$(CONFIG_MDCT) += arm/mdct_vfp.o
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VFP-OBJS-$(HAVE_ARMV6) += arm/fmtconvert_vfp.o
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@ -24,6 +24,8 @@
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#include "libavutil/attributes.h"
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#include "libavcodec/dcadsp.h"
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void ff_dca_lfe_fir_vfp(float *out, const float *in, const float *coefs,
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int decifactor, float scale);
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void ff_dca_lfe_fir_neon(float *out, const float *in, const float *coefs,
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int decifactor, float scale);
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@ -31,6 +33,8 @@ av_cold void ff_dcadsp_init_arm(DCADSPContext *s)
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{
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int cpu_flags = av_get_cpu_flags();
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if (have_vfp(cpu_flags) && !have_vfpv3(cpu_flags))
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s->lfe_fir = ff_dca_lfe_fir_vfp;
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if (have_neon(cpu_flags))
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s->lfe_fir = ff_dca_lfe_fir_neon;
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}
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220
libavcodec/arm/dcadsp_vfp.S
Normal file
220
libavcodec/arm/dcadsp_vfp.S
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@ -0,0 +1,220 @@
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/*
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* Copyright (c) 2013 RISC OS Open Ltd
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* Author: Ben Avison <bavison@riscosopen.org>
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/arm/asm.S"
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POUT .req a1
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PIN .req a2
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PCOEF .req a3
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DECIFACTOR .req a4
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OLDFPSCR .req a4
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COUNTER .req ip
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SCALE32 .req s28 @ use vector of 4 in place of 9th scalar when decifactor=32 / JMAX=8
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SCALE64 .req s0 @ spare register in scalar bank when decifactor=64 / JMAX=4
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IN0 .req s4
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IN1 .req s5
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IN2 .req s6
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IN3 .req s7
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IN4 .req s0
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IN5 .req s1
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IN6 .req s2
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IN7 .req s3
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COEF0 .req s8 @ coefficient elements
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COEF1 .req s9
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COEF2 .req s10
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COEF3 .req s11
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COEF4 .req s12
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COEF5 .req s13
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COEF6 .req s14
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COEF7 .req s15
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ACCUM0 .req s16 @ double-buffered multiply-accumulate results
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ACCUM4 .req s20
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POST0 .req s24 @ do long-latency post-multiply in this vector in parallel
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POST1 .req s25
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POST2 .req s26
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POST3 .req s27
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.macro inner_loop decifactor, dir, tail, head
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.ifc "\dir","up"
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.set X, 0
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.set Y, 4
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.else
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.set X, 4*JMAX*4 - 4
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.set Y, -4
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.endif
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.ifnc "\head",""
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vldr COEF0, [PCOEF, #X + (0*JMAX + 0) * Y]
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vldr COEF1, [PCOEF, #X + (1*JMAX + 0) * Y]
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vldr COEF2, [PCOEF, #X + (2*JMAX + 0) * Y]
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vldr COEF3, [PCOEF, #X + (3*JMAX + 0) * Y]
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.endif
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.ifnc "\tail",""
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vadd.f POST0, ACCUM0, ACCUM4 @ vector operation
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.endif
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.ifnc "\head",""
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vmul.f ACCUM0, COEF0, IN0 @ vector = vector * scalar
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vldr COEF4, [PCOEF, #X + (0*JMAX + 1) * Y]
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vldr COEF5, [PCOEF, #X + (1*JMAX + 1) * Y]
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vldr COEF6, [PCOEF, #X + (2*JMAX + 1) * Y]
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.endif
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.ifnc "\tail",""
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vmul.f POST0, POST0, SCALE\decifactor @ vector operation (SCALE may be scalar)
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.endif
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.ifnc "\head",""
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vldr COEF7, [PCOEF, #X + (3*JMAX + 1) * Y]
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.ifc "\tail",""
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vmul.f ACCUM4, COEF4, IN1 @ vector operation
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.endif
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vldr COEF0, [PCOEF, #X + (0*JMAX + 2) * Y]
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vldr COEF1, [PCOEF, #X + (1*JMAX + 2) * Y]
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.ifnc "\tail",""
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vmul.f ACCUM4, COEF4, IN1 @ vector operation
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.endif
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vldr COEF2, [PCOEF, #X + (2*JMAX + 2) * Y]
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vldr COEF3, [PCOEF, #X + (3*JMAX + 2) * Y]
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.endif
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.ifnc "\tail",""
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vstmia POUT!, {POST0-POST3}
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.endif
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.ifnc "\head",""
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vmla.f ACCUM0, COEF0, IN2 @ vector = vector * scalar
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vldr COEF4, [PCOEF, #X + (0*JMAX + 3) * Y]
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vldr COEF5, [PCOEF, #X + (1*JMAX + 3) * Y]
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vldr COEF6, [PCOEF, #X + (2*JMAX + 3) * Y]
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vldr COEF7, [PCOEF, #X + (3*JMAX + 3) * Y]
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vmla.f ACCUM4, COEF4, IN3 @ vector = vector * scalar
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.if \decifactor == 32
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vldr COEF0, [PCOEF, #X + (0*JMAX + 4) * Y]
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vldr COEF1, [PCOEF, #X + (1*JMAX + 4) * Y]
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vldr COEF2, [PCOEF, #X + (2*JMAX + 4) * Y]
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vldr COEF3, [PCOEF, #X + (3*JMAX + 4) * Y]
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vmla.f ACCUM0, COEF0, IN4 @ vector = vector * scalar
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vldr COEF4, [PCOEF, #X + (0*JMAX + 5) * Y]
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vldr COEF5, [PCOEF, #X + (1*JMAX + 5) * Y]
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vldr COEF6, [PCOEF, #X + (2*JMAX + 5) * Y]
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vldr COEF7, [PCOEF, #X + (3*JMAX + 5) * Y]
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vmla.f ACCUM4, COEF4, IN5 @ vector = vector * scalar
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vldr COEF0, [PCOEF, #X + (0*JMAX + 6) * Y]
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vldr COEF1, [PCOEF, #X + (1*JMAX + 6) * Y]
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vldr COEF2, [PCOEF, #X + (2*JMAX + 6) * Y]
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vldr COEF3, [PCOEF, #X + (3*JMAX + 6) * Y]
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vmla.f ACCUM0, COEF0, IN6 @ vector = vector * scalar
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vldr COEF4, [PCOEF, #X + (0*JMAX + 7) * Y]
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vldr COEF5, [PCOEF, #X + (1*JMAX + 7) * Y]
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vldr COEF6, [PCOEF, #X + (2*JMAX + 7) * Y]
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vldr COEF7, [PCOEF, #X + (3*JMAX + 7) * Y]
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vmla.f ACCUM4, COEF4, IN7 @ vector = vector * scalar
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.endif
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.endif
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.endm
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.macro dca_lfe_fir decifactor
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.if \decifactor == 32
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.set JMAX, 8
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vpush {s16-s31}
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vmov SCALE32, s0 @ duplicate scalar across vector
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vldr IN4, [PIN, #-4*4]
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vldr IN5, [PIN, #-5*4]
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vldr IN6, [PIN, #-6*4]
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vldr IN7, [PIN, #-7*4]
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.else
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.set JMAX, 4
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vpush {s16-s27}
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.endif
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mov COUNTER, #\decifactor/4 - 1
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inner_loop \decifactor, up,, head
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1: add PCOEF, PCOEF, #4*JMAX*4
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subs COUNTER, COUNTER, #1
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inner_loop \decifactor, up, tail, head
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bne 1b
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inner_loop \decifactor, up, tail
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mov COUNTER, #\decifactor/4 - 1
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inner_loop \decifactor, down,, head
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1: sub PCOEF, PCOEF, #4*JMAX*4
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subs COUNTER, COUNTER, #1
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inner_loop \decifactor, down, tail, head
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bne 1b
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inner_loop \decifactor, down, tail
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.if \decifactor == 32
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vpop {s16-s31}
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.else
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vpop {s16-s27}
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.endif
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fmxr FPSCR, OLDFPSCR
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bx lr
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.endm
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/* void ff_dca_lfe_fir_vfp(float *out, const float *in, const float *coefs,
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* int decifactor, float scale)
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*/
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function ff_dca_lfe_fir_vfp, export=1
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teq DECIFACTOR, #32
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fmrx OLDFPSCR, FPSCR
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ldr ip, =0x03030000 @ RunFast mode, short vectors of length 4, stride 1
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fmxr FPSCR, ip
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NOVFP vldr s0, [sp]
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vldr IN0, [PIN, #-0*4]
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vldr IN1, [PIN, #-1*4]
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vldr IN2, [PIN, #-2*4]
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vldr IN3, [PIN, #-3*4]
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beq 32f
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64: dca_lfe_fir 64
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.ltorg
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32: dca_lfe_fir 32
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endfunc
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.unreq POUT
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.unreq PIN
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.unreq PCOEF
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.unreq DECIFACTOR
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.unreq OLDFPSCR
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.unreq COUNTER
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.unreq SCALE32
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.unreq SCALE64
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.unreq IN0
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.unreq IN1
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.unreq IN2
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.unreq IN3
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.unreq IN4
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.unreq IN5
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.unreq IN6
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.unreq IN7
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.unreq COEF0
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.unreq COEF1
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.unreq COEF2
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.unreq COEF3
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.unreq COEF4
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.unreq COEF5
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.unreq COEF6
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.unreq COEF7
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.unreq ACCUM0
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.unreq ACCUM4
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.unreq POST0
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.unreq POST1
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.unreq POST2
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.unreq POST3
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