ppc: dsputil: Drop some unnecessary parentheses
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022184a646
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8bd6f88266
@ -612,14 +612,14 @@ static void add_bytes_altivec(uint8_t *dst, uint8_t *src, int w)
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register vector unsigned char vdst, vsrc;
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register vector unsigned char vdst, vsrc;
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/* dst and src are 16 bytes-aligned (guaranteed). */
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/* dst and src are 16 bytes-aligned (guaranteed). */
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for (i = 0; (i + 15) < w; i += 16) {
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for (i = 0; i + 15 < w; i += 16) {
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vdst = vec_ld(i, (unsigned char *) dst);
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vdst = vec_ld(i, (unsigned char *) dst);
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vsrc = vec_ld(i, (unsigned char *) src);
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vsrc = vec_ld(i, (unsigned char *) src);
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vdst = vec_add(vsrc, vdst);
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vdst = vec_add(vsrc, vdst);
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vec_st(vdst, i, (unsigned char *) dst);
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vec_st(vdst, i, (unsigned char *) dst);
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}
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}
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/* If w is not a multiple of 16. */
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/* If w is not a multiple of 16. */
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for (; (i < w); i++)
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for (; i < w; i++)
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dst[i] = src[i];
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dst[i] = src[i];
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}
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}
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@ -658,10 +658,10 @@ static int hadamard8_diff8x8_altivec(/* MpegEncContext */ void *s, uint8_t *dst,
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register vector signed short srcV, dstV; \
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register vector signed short srcV, dstV; \
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register vector signed short but0, but1, but2, op1, op2, op3; \
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register vector signed short but0, but1, but2, op1, op2, op3; \
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src1 = vec_ld(stride * i, src); \
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src1 = vec_ld(stride * i, src); \
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src2 = vec_ld((stride * i) + 15, src); \
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src2 = vec_ld(stride * i + 15, src); \
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srcO = vec_perm(src1, src2, vec_lvsl(stride * i, src)); \
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srcO = vec_perm(src1, src2, vec_lvsl(stride * i, src)); \
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dst1 = vec_ld(stride * i, dst); \
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dst1 = vec_ld(stride * i, dst); \
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dst2 = vec_ld((stride * i) + 15, dst); \
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dst2 = vec_ld(stride * i + 15, dst); \
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dstO = vec_perm(dst1, dst2, vec_lvsl(stride * i, dst)); \
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dstO = vec_perm(dst1, dst2, vec_lvsl(stride * i, dst)); \
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/* Promote the unsigned chars to signed shorts. */ \
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/* Promote the unsigned chars to signed shorts. */ \
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/* We're in the 8x8 function, we only care for the first 8. */ \
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/* We're in the 8x8 function, we only care for the first 8. */ \
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@ -828,10 +828,10 @@ static int hadamard8_diff16x8_altivec(/* MpegEncContext */ void *s, uint8_t *dst
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op3S __asm__ ("v30"); \
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op3S __asm__ ("v30"); \
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\
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\
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src1 = vec_ld(stride * i, src); \
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src1 = vec_ld(stride * i, src); \
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src2 = vec_ld((stride * i) + 16, src); \
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src2 = vec_ld(stride * i + 16, src); \
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srcO = vec_perm(src1, src2, vec_lvsl(stride * i, src)); \
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srcO = vec_perm(src1, src2, vec_lvsl(stride * i, src)); \
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dst1 = vec_ld(stride * i, dst); \
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dst1 = vec_ld(stride * i, dst); \
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dst2 = vec_ld((stride * i) + 16, dst); \
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dst2 = vec_ld(stride * i + 16, dst); \
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dstO = vec_perm(dst1, dst2, vec_lvsl(stride * i, dst)); \
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dstO = vec_perm(dst1, dst2, vec_lvsl(stride * i, dst)); \
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/* Promote the unsigned chars to signed shorts. */ \
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/* Promote the unsigned chars to signed shorts. */ \
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srcV = (vector signed short) vec_mergeh((vector signed char) vzero, \
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srcV = (vector signed short) vec_mergeh((vector signed char) vzero, \
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@ -51,7 +51,7 @@
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*/
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*/
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static void clear_blocks_dcbz32_ppc(int16_t *blocks)
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static void clear_blocks_dcbz32_ppc(int16_t *blocks)
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{
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{
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register int misal = ((unsigned long) blocks & 0x00000010);
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register int misal = (unsigned long) blocks & 0x00000010;
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register int i = 0;
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register int i = 0;
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if (misal) {
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if (misal) {
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@ -77,7 +77,7 @@ static void clear_blocks_dcbz32_ppc(int16_t *blocks)
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#if HAVE_DCBZL
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#if HAVE_DCBZL
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static void clear_blocks_dcbz128_ppc(int16_t *blocks)
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static void clear_blocks_dcbz128_ppc(int16_t *blocks)
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{
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{
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register int misal = ((unsigned long) blocks & 0x0000007f);
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register int misal = (unsigned long) blocks & 0x0000007f;
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register int i = 0;
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register int i = 0;
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if (misal) {
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if (misal) {
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@ -113,7 +113,7 @@ static long check_dcbzl_effect(void)
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if (!fakedata)
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if (!fakedata)
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return 0L;
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return 0L;
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fakedata_middle = (fakedata + 512);
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fakedata_middle = fakedata + 512;
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memset(fakedata, 0xFF, 1024);
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memset(fakedata, 0xFF, 1024);
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