configure: build fix for P5600 with mips code restructuring
Note:- backporting commit 15ef98afd10b3696d29fb6d19606ba03a9dd47ad from head Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com> Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
This commit is contained in:
Shivraj Patil
Michael Niedermayer
parent
a5638dbfba
commit
83eaaae005
184
configure
vendored
184
configure
vendored
@ -913,6 +913,25 @@ void foo(void){ __asm__ volatile($code); }
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EOF
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EOF
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}
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}
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check_inline_asm_flags(){
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log check_inline_asm_flags "$@"
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name="$1"
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code="$2"
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flags=''
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shift 2
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while [ "$1" != "" ]; do
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append flags $1
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shift
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done;
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disable $name
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cat > $TMPC <<EOF
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void foo(void){ __asm__ volatile($code); }
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EOF
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log_file $TMPC
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check_cmd $cc $CPPFLAGS $CFLAGS $flags "$@" $CC_C $(cc_o $TMPO) $TMPC &&
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enable $name && add_cflags $flags && add_asflags $flags && add_ldflags $flags
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}
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check_insn(){
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check_insn(){
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log check_insn "$@"
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log check_insn "$@"
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check_inline_asm ${1}_inline "\"$2\""
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check_inline_asm ${1}_inline "\"$2\""
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@ -1657,6 +1676,7 @@ ARCH_EXT_LIST_ARM="
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ARCH_EXT_LIST_MIPS="
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ARCH_EXT_LIST_MIPS="
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mipsfpu
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mipsfpu
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mips32r2
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mips32r2
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mips32r5
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mips64r2
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mips64r2
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mips32r6
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mips32r6
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mips64r6
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mips64r6
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@ -2150,10 +2170,11 @@ mipsfpu_deps="mips"
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mipsdsp_deps="mips"
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mipsdsp_deps="mips"
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mipsdspr2_deps="mips"
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mipsdspr2_deps="mips"
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mips32r2_deps="mips"
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mips32r2_deps="mips"
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mips32r5_deps="mips"
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mips32r6_deps="mips"
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mips32r6_deps="mips"
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mips64r2_deps="mips"
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mips64r2_deps="mips"
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mips64r6_deps="mips"
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mips64r6_deps="mips"
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msa_deps="mips"
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msa_deps="mipsfpu"
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mmi_deps="mips"
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mmi_deps="mips"
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altivec_deps="ppc"
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altivec_deps="ppc"
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@ -4153,82 +4174,27 @@ elif enabled mips; then
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cpuflags="-march=$cpu"
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cpuflags="-march=$cpu"
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case $cpu in
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if [ "$cpu" != "generic" ]; then
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24kc)
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disable mips32r6
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disable mips64r2
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disable mips64r6
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disable mipsfpu
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disable mipsdsp
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disable mipsdspr2
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disable msa
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;;
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24kf*)
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disable mips32r6
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disable mips64r2
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disable mips64r6
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disable mipsdsp
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disable mipsdspr2
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disable msa
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;;
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24kec|34kc|1004kc)
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disable mips32r6
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disable mips64r2
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disable mips64r6
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disable mipsfpu
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disable mipsdspr2
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disable msa
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;;
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24kef*|34kf*|1004kf*)
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disable mips32r6
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disable mips64r2
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disable mips64r6
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disable mipsdspr2
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disable msa
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;;
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74kc)
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disable mips32r6
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disable mips64r2
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disable mips64r6
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disable mipsfpu
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disable msa
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;;
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74kf)
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disable mips32r6
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disable mips64r2
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disable mips64r6
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disable msa
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;;
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p5600)
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disable mips32r6
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disable mips64r2
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disable mips64r6
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disable mipsdsp
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disable mipsdspr2
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check_cflags "-mtune=p5600" &&
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check_cflags "-mfp64 -msched-weight -mload-store-pairs -funroll-loops" &&
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add_asflags "-mfp64"
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;;
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i6400)
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disable mips32r2
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disable mips32r2
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disable mips32r6
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disable mips32r5
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disable mips64r2
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disable mips64r2
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disable mips32r6
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disable mips64r6
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disable loongson2
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disable loongson3
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case $cpu in
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24kc|24kf*|24kec|34kc|1004kc|24kef*|34kf*|1004kf*|74kc|74kf)
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enable mips32r2
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disable msa
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;;
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p5600|i6400)
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disable mipsdsp
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disable mipsdsp
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disable mipsdspr2
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disable mipsdspr2
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check_cflags "-mtune=i6400 -mabi=64" &&
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check_cflags "-mfp64 -msched-weight -mload-store-pairs -funroll-loops" &&
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check_ldflags "-mabi=64" &&
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add_asflags "-mfp64"
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;;
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;;
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loongson*)
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loongson*)
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disable mips32r2
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enable loongson2
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disable mips32r6
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enable loongson3
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disable mips64r2
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disable mips64r6
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disable mipsfpu
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disable mipsdsp
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disable mipsdspr2
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disable msa
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enable local_aligned_8 local_aligned_16 local_aligned_32
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enable local_aligned_8 local_aligned_16 local_aligned_32
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enable simd_align_16
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enable simd_align_16
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enable fast_64bit
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enable fast_64bit
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@ -4248,24 +4214,51 @@ elif enabled mips; then
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;;
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;;
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esac
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esac
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;;
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;;
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generic)
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disable mips64r6
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disable msa
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;;
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*)
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*)
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# Unknown CPU. Disable everything.
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# Unknown CPU. Disable everything.
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warn "unknown CPU. Disabling all MIPS optimizations."
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warn "unknown CPU. Disabling all MIPS optimizations."
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disable mipsfpu
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disable mipsfpu
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disable mips32r2
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disable mips32r6
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disable mips64r2
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disable mips64r6
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disable mipsdsp
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disable mipsdsp
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disable mipsdspr2
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disable mipsdspr2
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disable msa
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disable msa
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disable mmi
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;;
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;;
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esac
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esac
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case $cpu in
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24kc)
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disable mipsfpu
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disable mipsdsp
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disable mipsdspr2
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;;
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24kf*)
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disable mipsdsp
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disable mipsdspr2
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;;
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24kec|34kc|1004kc)
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disable mipsfpu
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disable mipsdspr2
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;;
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24kef*|34kf*|1004kf*)
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disable mipsdspr2
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;;
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74kc)
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disable mipsfpu
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;;
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p5600)
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enable mips32r5
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check_cflags "-mtune=p5600" && check_cflags "-msched-weight -mload-store-pairs -funroll-loops"
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;;
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i6400)
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enable mips64r6
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check_cflags "-mtune=i6400 -mabi=64" && check_cflags "-msched-weight -mload-store-pairs -funroll-loops" && check_ldflags "-mabi=64"
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;;
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esac
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else
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# We do not disable anything. Is up to the user to disable the unwanted features.
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warn 'generic cpu selected'
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fi
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elif enabled ppc; then
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elif enabled ppc; then
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disable ldbrx
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disable ldbrx
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@ -5073,27 +5066,22 @@ elif enabled mips; then
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enabled mmi && check_inline_asm mmi '"punpcklhw $f0, $f0, $f0"'
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enabled mmi && check_inline_asm mmi '"punpcklhw $f0, $f0, $f0"'
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# Enable minimum ISA based on selected options
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# Enable minimum ISA based on selected options
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if enabled mips64 && (enabled mipsdsp || enabled mipsdspr2); then
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if enabled mips64; then
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add_cflags "-mips64r2"
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enabled mips64r6 && check_inline_asm_flags mips64r6 '"dlsa $0, $0, $0, 1"' '-mips64r6'
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add_asflags "-mips64r2"
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enabled mips64r2 && check_inline_asm_flags mips64r2 '"dext $0, $0, 0, 1"' '-mips64r2'
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elif enabled mips64 && enabled mipsfpu && disabled loongson2 && disabled loongson3; then
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disabled mips64r6 && disabled mips64r2 && check_inline_asm_flags mips64r1 '"daddi $0, $0, 0"' '-mips64'
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add_cflags "-mips64"
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else
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add_asflags "-mips64"
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enabled mips32r6 && check_inline_asm_flags mips32r6 '"aui $0, $0, 0"' '-mips32r6'
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elif enabled mipsdsp || enabled mipsdspr2; then
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enabled mips32r5 && check_inline_asm_flags mips32r5 '"eretnc"' '-mips32r5'
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add_cflags "-mips32r2 -mfp32"
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enabled mips32r2 && check_inline_asm_flags mips32r2 '"ext $0, $0, 0, 1"' '-mips32r2'
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add_asflags "-mips32r2 -mfp32"
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disabled mips32r6 && disabled mips32r5 && disabled mips32r2 && check_inline_asm_flags mips32r1 '"addi $0, $0, 0"' '-mips32'
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fi
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fi
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enabled mipsdsp && add_cflags "-mdsp" && add_asflags "-mdsp" &&
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enabled mipsfpu && check_inline_asm_flags mipsfpu '"cvt.d.l $f0, $f2"' '-mhard-float'
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check_inline_asm mipsdsp '"addu.qb $t0, $t1, $t2"'
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enabled mipsfpu && (enabled mips32r5 || enabled mips32r6 || enabled mips64r6) && check_inline_asm_flags mipsfpu '"cvt.d.l $f0, $f1"' '-mfp64'
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enabled mipsdspr2 && add_cflags "-mdspr2" && add_asflags "-mdspr2" &&
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enabled mipsfpu && enabled msa && check_inline_asm_flags msa '"addvi.b $w0, $w1, 1"' '-mmsa' && check_header msa.h || disable msa
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check_inline_asm mipsdspr2 '"absq_s.qb $t0, $t1"'
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enabled mipsdsp && check_inline_asm_flags mipsdsp '"addu.qb $t0, $t1, $t2"' '-mdsp'
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enabled mipsfpu && add_cflags "-mhard-float" && add_asflags "-mhard-float" &&
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enabled mipsdspr2 && check_inline_asm_flags mipsdspr2 '"absq_s.qb $t0, $t1"' '-mdspr2'
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check_inline_asm mipsfpu '"madd.d $f0, $f2, $f4, $f6"'
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enabled msa && check_cflags "-mmsa" && check_ldflags "-mmsa" &&
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check_inline_asm msa '"addvi.b $w0, $w1, 1"'
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enabled msa && add_asflags "-mmsa"
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elif enabled parisc; then
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elif enabled parisc; then
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