Merge commit 'd6e4f5fef0d811e180fd7541941e07dca9e11dc0'
* commit 'd6e4f5fef0d811e180fd7541941e07dca9e11dc0': arm: Add VFP-accelerated version of int32_to_float_fmul_array8 Merged-by: Michael Niedermayer <michaelni@gmx.at>
This commit is contained in:
Michael Niedermayer
commit
3cab228005
@ -30,6 +30,9 @@ void ff_int32_to_float_fmul_scalar_neon(float *dst, const int32_t *src,
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void ff_int32_to_float_fmul_scalar_vfp(float *dst, const int32_t *src,
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void ff_int32_to_float_fmul_scalar_vfp(float *dst, const int32_t *src,
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float mul, int len);
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float mul, int len);
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void ff_int32_to_float_fmul_array8_vfp(FmtConvertContext *c, float *dst,
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const int32_t *src, const float *mul,
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int len);
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void ff_float_to_int16_neon(int16_t *dst, const float *src, long len);
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void ff_float_to_int16_neon(int16_t *dst, const float *src, long len);
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void ff_float_to_int16_interleave_neon(int16_t *, const float **, long, int);
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void ff_float_to_int16_interleave_neon(int16_t *, const float **, long, int);
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@ -42,10 +45,11 @@ av_cold void ff_fmt_convert_init_arm(FmtConvertContext *c, AVCodecContext *avctx
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if (have_vfp(cpu_flags) && have_armv6(cpu_flags)) {
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if (have_vfp(cpu_flags) && have_armv6(cpu_flags)) {
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if (!have_vfpv3(cpu_flags)) {
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if (!have_vfpv3(cpu_flags)) {
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// This function doesn't use anything armv6 specific in itself,
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// These functions don't use anything armv6 specific in themselves,
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// but ff_float_to_int16_vfp which is in the same assembly source
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// but ff_float_to_int16_vfp which is in the same assembly source
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// file does, thus the whole file requires armv6 to be built.
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// file does, thus the whole file requires armv6 to be built.
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c->int32_to_float_fmul_scalar = ff_int32_to_float_fmul_scalar_vfp;
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c->int32_to_float_fmul_scalar = ff_int32_to_float_fmul_scalar_vfp;
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c->int32_to_float_fmul_array8 = ff_int32_to_float_fmul_array8_vfp;
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}
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}
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c->float_to_int16 = ff_float_to_int16_vfp;
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c->float_to_int16 = ff_float_to_int16_vfp;
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@ -83,6 +83,168 @@ endfunc
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* Assume len is a multiple of 8, destination buffer is at least 4 bytes aligned
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* Assume len is a multiple of 8, destination buffer is at least 4 bytes aligned
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* (16 bytes alignment is best for BCM2835), little-endian.
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* (16 bytes alignment is best for BCM2835), little-endian.
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*/
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*/
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@ void ff_int32_to_float_fmul_array8_vfp(FmtConvertContext *c, float *dst, const int32_t *src, const float *mul, int len)
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function ff_int32_to_float_fmul_array8_vfp, export=1
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push {lr}
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ldr a1, [sp, #4]
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subs lr, a1, #3*8
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bcc 50f @ too short to pipeline
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@ Now need to find (len / 8) % 3. The approximation
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@ x / 24 = (x * 0xAB) >> 12
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@ is good for x < 4096, which is true for both AC3 and DCA.
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mov a1, #0xAB
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ldr ip, =0x03070000 @ RunFast mode, short vectors of length 8, stride 1
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mul a1, lr, a1
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vpush {s16-s31}
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mov a1, a1, lsr #12
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add a1, a1, a1, lsl #1
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rsb a1, a1, lr, lsr #3
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cmp a1, #1
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fmrx a1, FPSCR
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fmxr FPSCR, ip
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beq 11f
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blo 10f
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@ Array is (2 + multiple of 3) x 8 floats long
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@ drop through...
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vldmia a3!, {s16-s23}
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vldmia a4!, {s2,s3}
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vldmia a3!, {s24-s31}
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vcvt.f32.s32 s16, s16
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vcvt.f32.s32 s17, s17
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vcvt.f32.s32 s18, s18
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vcvt.f32.s32 s19, s19
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vcvt.f32.s32 s20, s20
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vcvt.f32.s32 s21, s21
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vcvt.f32.s32 s22, s22
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vcvt.f32.s32 s23, s23
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vmul.f32 s16, s16, s2
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@ drop through...
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3:
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vldmia a3!, {s8-s15}
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vldmia a4!, {s1}
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vcvt.f32.s32 s24, s24
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vcvt.f32.s32 s25, s25
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vcvt.f32.s32 s26, s26
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vcvt.f32.s32 s27, s27
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vcvt.f32.s32 s28, s28
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vcvt.f32.s32 s29, s29
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vcvt.f32.s32 s30, s30
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vcvt.f32.s32 s31, s31
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vmul.f32 s24, s24, s3
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vstmia a2!, {s16-s19}
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vstmia a2!, {s20-s23}
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2:
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vldmia a3!, {s16-s23}
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vldmia a4!, {s2}
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vcvt.f32.s32 s8, s8
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vcvt.f32.s32 s9, s9
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vcvt.f32.s32 s10, s10
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vcvt.f32.s32 s11, s11
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vcvt.f32.s32 s12, s12
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vcvt.f32.s32 s13, s13
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vcvt.f32.s32 s14, s14
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vcvt.f32.s32 s15, s15
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vmul.f32 s8, s8, s1
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vstmia a2!, {s24-s27}
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vstmia a2!, {s28-s31}
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1:
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vldmia a3!, {s24-s31}
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vldmia a4!, {s3}
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vcvt.f32.s32 s16, s16
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vcvt.f32.s32 s17, s17
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vcvt.f32.s32 s18, s18
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vcvt.f32.s32 s19, s19
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vcvt.f32.s32 s20, s20
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vcvt.f32.s32 s21, s21
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vcvt.f32.s32 s22, s22
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vcvt.f32.s32 s23, s23
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vmul.f32 s16, s16, s2
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vstmia a2!, {s8-s11}
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vstmia a2!, {s12-s15}
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subs lr, lr, #8*3
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bpl 3b
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vcvt.f32.s32 s24, s24
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vcvt.f32.s32 s25, s25
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vcvt.f32.s32 s26, s26
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vcvt.f32.s32 s27, s27
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vcvt.f32.s32 s28, s28
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vcvt.f32.s32 s29, s29
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vcvt.f32.s32 s30, s30
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vcvt.f32.s32 s31, s31
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vmul.f32 s24, s24, s3
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vstmia a2!, {s16-s19}
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vstmia a2!, {s20-s23}
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vstmia a2!, {s24-s27}
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vstmia a2!, {s28-s31}
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fmxr FPSCR, a1
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vpop {s16-s31}
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pop {pc}
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10: @ Array is (multiple of 3) x 8 floats long
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vldmia a3!, {s8-s15}
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vldmia a4!, {s1,s2}
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vldmia a3!, {s16-s23}
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vcvt.f32.s32 s8, s8
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vcvt.f32.s32 s9, s9
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vcvt.f32.s32 s10, s10
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vcvt.f32.s32 s11, s11
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vcvt.f32.s32 s12, s12
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vcvt.f32.s32 s13, s13
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vcvt.f32.s32 s14, s14
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vcvt.f32.s32 s15, s15
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vmul.f32 s8, s8, s1
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b 1b
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11: @ Array is (1 + multiple of 3) x 8 floats long
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vldmia a3!, {s24-s31}
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vldmia a4!, {s3}
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vldmia a3!, {s8-s15}
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vldmia a4!, {s1}
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vcvt.f32.s32 s24, s24
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vcvt.f32.s32 s25, s25
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vcvt.f32.s32 s26, s26
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vcvt.f32.s32 s27, s27
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vcvt.f32.s32 s28, s28
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vcvt.f32.s32 s29, s29
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vcvt.f32.s32 s30, s30
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vcvt.f32.s32 s31, s31
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vmul.f32 s24, s24, s3
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b 2b
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50:
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ldr lr, =0x03070000 @ RunFast mode, short vectors of length 8, stride 1
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fmrx ip, FPSCR
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fmxr FPSCR, lr
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51:
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vldmia a3!, {s8-s15}
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vldmia a4!, {s0}
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vcvt.f32.s32 s8, s8
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vcvt.f32.s32 s9, s9
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vcvt.f32.s32 s10, s10
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vcvt.f32.s32 s11, s11
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vcvt.f32.s32 s12, s12
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vcvt.f32.s32 s13, s13
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vcvt.f32.s32 s14, s14
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vcvt.f32.s32 s15, s15
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vmul.f32 s8, s8, s0
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subs a1, a1, #8
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vstmia a2!, {s8-s11}
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vstmia a2!, {s12-s15}
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bne 51b
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fmxr FPSCR, ip
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pop {pc}
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endfunc
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/**
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* ARM VFP optimised int32 to float conversion.
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* Assume len is a multiple of 8, destination buffer is at least 4 bytes aligned
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* (16 bytes alignment is best for BCM2835), little-endian.
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* TODO: could be further optimised by unrolling and interleaving, as above
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*/
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@ void ff_int32_to_float_fmul_scalar_vfp(float *dst, const int32_t *src, float mul, int len)
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@ void ff_int32_to_float_fmul_scalar_vfp(float *dst, const int32_t *src, float mul, int len)
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function ff_int32_to_float_fmul_scalar_vfp, export=1
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function ff_int32_to_float_fmul_scalar_vfp, export=1
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VFP tmp .req a4
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VFP tmp .req a4
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