mips: port optimizations to mips n64
This mainly consists of replacing all the pointer arithmatic 'addiu' instructions with PTR_ADDIU which will handle the differences in pointer sizes when compiled on 64 bit mips systems. The header asmdefs.h contains the PTR_ macros which expend to the correct mips instructions to manipulate registers containing pointers. Signed-off-by: James Cowgill <james410@cowgill.org.uk> Reviewed-by: Nedeljko Babic <Nedeljko.Babic@imgtec.com> Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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committed by
Michael Niedermayer

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commit
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@@ -55,6 +55,8 @@
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#define AVCODEC_LSP_MIPS_H
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#if HAVE_MIPSFPU && HAVE_INLINE_ASM
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#include "libavutil/mips/asmdefs.h"
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static av_always_inline void ff_lsp2polyf_mips(const double *lsp, double *f, int lp_half_order)
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{
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int i, j = 0;
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@@ -73,7 +75,7 @@ static av_always_inline void ff_lsp2polyf_mips(const double *lsp, double *f, int
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__asm__ volatile(
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"move %[p_f], %[p_fi] \n\t"
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"add.d %[val], %[val], %[val] \n\t"
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"addiu %[p_fi], 8 \n\t"
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PTR_ADDIU "%[p_fi], 8 \n\t"
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"ldc1 %[f_j_1], 0(%[p_f]) \n\t"
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"ldc1 %[f_j], 8(%[p_f]) \n\t"
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"neg.d %[val], %[val] \n\t"
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@@ -91,7 +93,7 @@ static av_always_inline void ff_lsp2polyf_mips(const double *lsp, double *f, int
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"mov.d %[f_j_1], %[f_j_2] \n\t"
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"ldc1 %[f_j_2], -16(%[p_f]) \n\t"
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"sdc1 %[tmp], 8(%[p_f]) \n\t"
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"addiu %[p_f], -8 \n\t"
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PTR_ADDIU "%[p_f], -8 \n\t"
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"bgtz %[j], ff_lsp2polyf_lp_j%= \n\t"
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"ff_lsp2polyf_lp_j_end%=: \n\t"
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