x86/hevcdsp: add ff_hevc_sao_edge_filter_{10,12}_{sse2,avx2}
Original x86 intrinsics code by Pierre-Edouard Lepere. Yasm port, refactoring and optimizations by James Almer. Benchmarks of BQTerrace_1920x1080_60_qp22.bin with an Intel Core i5-4200U Width 32 342694 decicycles in sao_edge_filter_10, 16384 runs, 0 skips 29476 decicycles in ff_hevc_sao_edge_filter_32_10_ssse3, 16384 runs, 0 skips 13996 decicycles in ff_hevc_sao_edge_filter_32_10_avx2, 16381 runs, 3 skips Width 64 581163 decicycles in sao_edge_filter_10, 8192 runs, 0 skips 59774 decicycles in ff_hevc_sao_edge_filter_64_10_ssse3, 8192 runs, 0 skips 28383 decicycles in ff_hevc_sao_edge_filter_64_10_avx2, 8191 runs, 1 skips Signed-off-by: James Almer <jamrial@gmail.com>
This commit is contained in:
James Almer
parent
042c1159fc
commit
15574c505b
@ -22,8 +22,10 @@
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#include "libavutil/x86/asm.h" // for xmm_reg
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#include "constants.h"
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DECLARE_ALIGNED(16, const xmm_reg, ff_pw_1) = { 0x0001000100010001ULL, 0x0001000100010001ULL };
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DECLARE_ALIGNED(16, const xmm_reg, ff_pw_2) = { 0x0002000200020002ULL, 0x0002000200020002ULL };
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DECLARE_ALIGNED(32, const ymm_reg, ff_pw_1) = { 0x0001000100010001ULL, 0x0001000100010001ULL,
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0x0001000100010001ULL, 0x0001000100010001ULL };
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DECLARE_ALIGNED(32, const ymm_reg, ff_pw_2) = { 0x0002000200020002ULL, 0x0002000200020002ULL,
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0x0002000200020002ULL, 0x0002000200020002ULL };
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DECLARE_ALIGNED(16, const xmm_reg, ff_pw_3) = { 0x0003000300030003ULL, 0x0003000300030003ULL };
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DECLARE_ALIGNED(16, const xmm_reg, ff_pw_4) = { 0x0004000400040004ULL, 0x0004000400040004ULL };
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DECLARE_ALIGNED(16, const xmm_reg, ff_pw_5) = { 0x0005000500050005ULL, 0x0005000500050005ULL };
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@ -48,7 +50,8 @@ DECLARE_ALIGNED(16, const xmm_reg, ff_pw_1019) = { 0x03FB03FB03FB03FBULL, 0x03F
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DECLARE_ALIGNED(16, const xmm_reg, ff_pw_1024) = { 0x0400040004000400ULL, 0x0400040004000400ULL };
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DECLARE_ALIGNED(16, const xmm_reg, ff_pw_2048) = { 0x0800080008000800ULL, 0x0800080008000800ULL };
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DECLARE_ALIGNED(16, const xmm_reg, ff_pw_8192) = { 0x2000200020002000ULL, 0x2000200020002000ULL };
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DECLARE_ALIGNED(16, const xmm_reg, ff_pw_m1) = { 0xFFFFFFFFFFFFFFFFULL, 0xFFFFFFFFFFFFFFFFULL };
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DECLARE_ALIGNED(32, const ymm_reg, ff_pw_m1) = { 0xFFFFFFFFFFFFFFFFULL, 0xFFFFFFFFFFFFFFFFULL,
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0xFFFFFFFFFFFFFFFFULL, 0xFFFFFFFFFFFFFFFFULL };
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DECLARE_ALIGNED(16, const xmm_reg, ff_pb_0) = { 0x0000000000000000ULL, 0x0000000000000000ULL };
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DECLARE_ALIGNED(32, const ymm_reg, ff_pb_1) = { 0x0101010101010101ULL, 0x0101010101010101ULL,
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@ -25,8 +25,8 @@
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#include "libavutil/x86/asm.h"
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extern const xmm_reg ff_pw_1;
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extern const xmm_reg ff_pw_2;
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extern const ymm_reg ff_pw_1;
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extern const ymm_reg ff_pw_2;
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extern const xmm_reg ff_pw_3;
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extern const xmm_reg ff_pw_4;
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extern const xmm_reg ff_pw_5;
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@ -47,7 +47,7 @@ extern const xmm_reg ff_pw_512;
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extern const xmm_reg ff_pw_1024;
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extern const xmm_reg ff_pw_2048;
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extern const xmm_reg ff_pw_8192;
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extern const xmm_reg ff_pw_m1;
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extern const ymm_reg ff_pw_m1;
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extern const ymm_reg ff_pb_1;
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extern const ymm_reg ff_pb_3;
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@ -28,8 +28,12 @@ SECTION_RODATA 32
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pw_mask10: times 16 dw 0x03FF
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pw_mask12: times 16 dw 0x0FFF
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pb_2: times 32 db 2
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pw_m2: times 16 dw -2
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pb_edge_shuffle: times 2 db 1, 2, 0, 3, 4, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
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pb_eo: db -1, 0, 1, 0, 0, -1, 0, 1, -1, -1, 1, 1, 1, -1, -1, 1
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cextern pw_m1
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cextern pw_1
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cextern pw_2
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cextern pb_1
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SECTION_TEXT
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@ -395,6 +399,158 @@ INIT_YMM cpuname
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RET
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%endmacro
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%macro PMINUW 4
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%if cpuflag(sse4)
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pminuw %1, %2, %3
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%else
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psubusw %4, %2, %3
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psubw %1, %2, %4
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%endif
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%endmacro
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%macro HEVC_SAO_EDGE_FILTER_COMPUTE_10 0
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PMINUW m4, m1, m2, m6
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PMINUW m5, m1, m3, m7
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pcmpeqw m2, m4
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pcmpeqw m3, m5
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pcmpeqw m4, m1
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pcmpeqw m5, m1
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psubw m4, m2
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psubw m5, m3
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paddw m4, m5
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pcmpeqw m2, m4, [pw_m2]
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pcmpeqw m3, m4, m13
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pcmpeqw m5, m4, m0
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pcmpeqw m6, m4, m14
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pcmpeqw m7, m4, m15
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pand m2, m8
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pand m3, m9
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pand m5, m10
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pand m6, m11
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pand m7, m12
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paddw m2, m3
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paddw m5, m6
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paddw m2, m7
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paddw m2, m1
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paddw m2, m5
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%endmacro
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;void ff_hevc_sao_edge_filter_<width>_<depth>_<opt>(uint8_t *_dst, uint8_t *_src, ptrdiff_t stride_dst, int16_t *sao_offset_val,
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; int eo, int width, int height);
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%macro HEVC_SAO_EDGE_FILTER_16 3
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%if WIN64
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cglobal hevc_sao_edge_filter_%2_%1, 4, 8, 16, dst, src, dststride, offset, a_stride, b_stride, height, tmp
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%define eoq heightq
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movsxd eoq, dword r4m
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movsx a_strideq, byte [pb_eo+eoq*4+1]
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movsx b_strideq, byte [pb_eo+eoq*4+3]
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imul a_strideq, EDGE_SRCSTRIDE>>1
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imul b_strideq, EDGE_SRCSTRIDE>>1
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movsx tmpq, byte [pb_eo+eoq*4]
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add a_strideq, tmpq
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movsx tmpq, byte [pb_eo+eoq*4+2]
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add b_strideq, tmpq
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mov heightd, r6m
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add a_strideq, a_strideq
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add b_strideq, b_strideq
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%else ; UNIX64
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cglobal hevc_sao_edge_filter_%2_%1, 5, 9, 16, dst, src, dststride, offset, eo, a_stride, b_stride, height, tmp
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%define tmp2q heightq
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movsxd eoq, eod
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lea tmp2q, [pb_eo]
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movsx a_strideq, byte [tmp2q+eoq*4+1]
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movsx b_strideq, byte [tmp2q+eoq*4+3]
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imul a_strideq, EDGE_SRCSTRIDE>>1
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imul b_strideq, EDGE_SRCSTRIDE>>1
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movsx tmpq, byte [tmp2q+eoq*4]
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add a_strideq, tmpq
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movsx tmpq, byte [tmp2q+eoq*4+2]
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add b_strideq, tmpq
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mov heightd, r6m
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add a_strideq, a_strideq
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add b_strideq, b_strideq
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%endif ; ARCH
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%if cpuflag(avx2)
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SPLATW m8, [offsetq+2]
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SPLATW m9, [offsetq+4]
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SPLATW m10, [offsetq+0]
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SPLATW m11, [offsetq+6]
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SPLATW m12, [offsetq+8]
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%else
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movq m10, [offsetq+0]
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movd m12, [offsetq+6]
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SPLATW m8, xm10, 1
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SPLATW m9, xm10, 2
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SPLATW m10, xm10, 0
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SPLATW m11, xm12, 0
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SPLATW m12, xm12, 1
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%endif
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pxor m0, m0
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mova m13, [pw_m1]
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mova m14, [pw_1]
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mova m15, [pw_2]
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align 16
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.loop
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%if %2 == 8
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mova m1, [srcq]
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movu m2, [srcq+a_strideq]
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movu m3, [srcq+b_strideq]
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HEVC_SAO_EDGE_FILTER_COMPUTE_10
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CLIPW m2, m0, [pw_mask %+ %1]
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mova [dstq], m2
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%endif
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%assign i 0
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%rep %3
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mova m1, [srcq + i]
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movu m2, [srcq+a_strideq + i]
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movu m3, [srcq+b_strideq + i]
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HEVC_SAO_EDGE_FILTER_COMPUTE_10
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CLIPW m2, m0, [pw_mask %+ %1]
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mova [dstq + i], m2
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mova m1, [srcq + i + mmsize]
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movu m2, [srcq+a_strideq + i + mmsize]
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movu m3, [srcq+b_strideq + i + mmsize]
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HEVC_SAO_EDGE_FILTER_COMPUTE_10
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CLIPW m2, m0, [pw_mask %+ %1]
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mova [dstq + i + mmsize], m2
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%assign i i+mmsize*2
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%endrep
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%if %2 == 48
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INIT_XMM cpuname
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mova m1, [srcq + i]
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movu m2, [srcq+a_strideq + i]
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movu m3, [srcq+b_strideq + i]
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HEVC_SAO_EDGE_FILTER_COMPUTE_10
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CLIPW m2, m0, [pw_mask %+ %1]
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mova [dstq + i], m2
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mova m1, [srcq + i + mmsize]
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movu m2, [srcq+a_strideq + i + mmsize]
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movu m3, [srcq+b_strideq + i + mmsize]
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HEVC_SAO_EDGE_FILTER_COMPUTE_10
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CLIPW m2, m0, [pw_mask %+ %1]
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mova [dstq + i + mmsize], m2
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%if cpuflag(avx2)
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INIT_YMM cpuname
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%endif
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%endif
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add dstq, dststrideq
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add srcq, EDGE_SRCSTRIDE
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dec heightd
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jg .loop
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RET
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%endmacro
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INIT_XMM ssse3
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HEVC_SAO_EDGE_FILTER_8 8, 0
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HEVC_SAO_EDGE_FILTER_8 16, 1, a
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@ -408,3 +564,29 @@ HEVC_SAO_EDGE_FILTER_8 32, 1, a
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HEVC_SAO_EDGE_FILTER_8 48, 1, u
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HEVC_SAO_EDGE_FILTER_8 64, 2, a
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%endif
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%if ARCH_X86_64
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INIT_XMM sse2
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HEVC_SAO_EDGE_FILTER_16 10, 8, 0
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HEVC_SAO_EDGE_FILTER_16 10, 16, 1
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HEVC_SAO_EDGE_FILTER_16 10, 32, 2
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HEVC_SAO_EDGE_FILTER_16 10, 48, 2
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HEVC_SAO_EDGE_FILTER_16 10, 64, 4
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HEVC_SAO_EDGE_FILTER_16 12, 8, 0
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HEVC_SAO_EDGE_FILTER_16 12, 16, 1
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HEVC_SAO_EDGE_FILTER_16 12, 32, 2
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HEVC_SAO_EDGE_FILTER_16 12, 48, 2
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HEVC_SAO_EDGE_FILTER_16 12, 64, 4
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%if HAVE_AVX2_EXTERNAL
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INIT_YMM avx2
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HEVC_SAO_EDGE_FILTER_16 10, 32, 1
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HEVC_SAO_EDGE_FILTER_16 10, 48, 1
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HEVC_SAO_EDGE_FILTER_16 10, 64, 2
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HEVC_SAO_EDGE_FILTER_16 12, 32, 1
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HEVC_SAO_EDGE_FILTER_16 12, 48, 1
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HEVC_SAO_EDGE_FILTER_16 12, 64, 2
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%endif
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%endif
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@ -522,6 +522,10 @@ void ff_hevc_sao_edge_filter_64_##bitd##_##opt(uint8_t *_dst, uint8_t *_src, ptr
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SAO_EDGE_FILTER_FUNCS(8, ssse3);
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SAO_EDGE_FILTER_FUNCS(8, avx2);
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SAO_EDGE_FILTER_FUNCS(10, sse2);
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SAO_EDGE_FILTER_FUNCS(10, avx2);
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SAO_EDGE_FILTER_FUNCS(12, sse2);
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SAO_EDGE_FILTER_FUNCS(12, avx2);
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#define SAO_EDGE_INIT(bitd, opt) do { \
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c->sao_edge_filter[0] = ff_hevc_sao_edge_filter_8_##bitd##_##opt; \
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@ -636,6 +640,7 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth)
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c->hevc_h_loop_filter_luma = ff_hevc_h_loop_filter_luma_10_sse2;
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SAO_BAND_INIT(10, sse2);
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SAO_EDGE_INIT(10, sse2);
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}
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c->idct_dc[1] = ff_hevc_idct8x8_dc_10_sse2;
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@ -677,6 +682,9 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth)
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c->idct_dc[3] = ff_hevc_idct32x32_dc_10_avx2;
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if (ARCH_X86_64) {
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SAO_BAND_INIT(10, avx2);
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c->sao_edge_filter[2] = ff_hevc_sao_edge_filter_32_10_avx2;
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c->sao_edge_filter[3] = ff_hevc_sao_edge_filter_48_10_avx2;
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c->sao_edge_filter[4] = ff_hevc_sao_edge_filter_64_10_avx2;
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}
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c->transform_add[2] = ff_hevc_transform_add16_10_avx2;
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@ -696,6 +704,7 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth)
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c->hevc_h_loop_filter_luma = ff_hevc_h_loop_filter_luma_12_sse2;
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SAO_BAND_INIT(12, sse2);
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SAO_EDGE_INIT(12, sse2);
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}
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c->idct_dc[1] = ff_hevc_idct8x8_dc_12_sse2;
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@ -732,6 +741,9 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth)
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c->idct_dc[3] = ff_hevc_idct32x32_dc_12_avx2;
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if (ARCH_X86_64) {
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SAO_BAND_INIT(12, avx2);
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c->sao_edge_filter[2] = ff_hevc_sao_edge_filter_32_12_avx2;
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c->sao_edge_filter[3] = ff_hevc_sao_edge_filter_48_12_avx2;
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c->sao_edge_filter[4] = ff_hevc_sao_edge_filter_64_12_avx2;
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}
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}
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}
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