x86/videodsp: add emulated_edge_mc_mmxext
This also changes hfix8_mmx and above to use mmx regs instead of gprs, and makes emulated_edge_mc_sse and emulated_edge_mc_sse2 use mmxext hfix and hvar functions instead of mmx where possible. This is mostly in preparation for an ssse3 version. Signed-off-by: James Almer <jamrial@gmail.com> code is about 1 cpu cycle faster approximately Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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@ -92,21 +92,13 @@ INIT_XMM sse
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vvar_fn
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vvar_fn
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%macro hvar_fn 0
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%macro hvar_fn 0
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cglobal emu_edge_hvar, 5, 6, 1, dst, dst_stride, start_x, n_words, h, w
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cglobal emu_edge_hvar, 5, 6, 2, dst, dst_stride, start_x, n_words, h, w
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lea dstq, [dstq+n_wordsq*2]
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lea dstq, [dstq+n_wordsq*2]
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neg n_wordsq
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neg n_wordsq
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lea start_xq, [start_xq+n_wordsq*2]
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lea start_xq, [start_xq+n_wordsq*2]
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.y_loop: ; do {
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.y_loop: ; do {
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; FIXME also write a ssse3 version using pshufb
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movzx wd, byte [dstq+start_xq] ; w = read(1)
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imul wd, 0x01010101 ; w *= 0x01010101
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movd m0, wd
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mov wq, n_wordsq ; initialize w
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mov wq, n_wordsq ; initialize w
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%if cpuflag(sse2)
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SPLATB_LOAD m0, dstq+start_xq, m1 ; read(1); splat
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pshufd m0, m0, q0000 ; splat
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%else ; mmx
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punpckldq m0, m0 ; splat
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%endif ; mmx/sse
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.x_loop: ; do {
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.x_loop: ; do {
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movu [dstq+wq*2], m0 ; write($reg, $mmsize)
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movu [dstq+wq*2], m0 ; write($reg, $mmsize)
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add wq, mmsize/2 ; w -= $mmsize/2
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add wq, mmsize/2 ; w -= $mmsize/2
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@ -122,6 +114,8 @@ cglobal emu_edge_hvar, 5, 6, 1, dst, dst_stride, start_x, n_words, h, w
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%if ARCH_X86_32
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%if ARCH_X86_32
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INIT_MMX mmx
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INIT_MMX mmx
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hvar_fn
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hvar_fn
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INIT_MMX mmxext
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hvar_fn
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%endif
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%endif
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INIT_XMM sse2
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INIT_XMM sse2
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@ -344,16 +338,12 @@ VERTICAL_EXTEND 16, 22
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; obviously not the same on both sides.
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; obviously not the same on both sides.
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%macro READ_V_PIXEL 2
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%macro READ_V_PIXEL 2
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movzx vald, byte %2
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%if notcpuflag(mmxext) && %1 < 8
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movzx vald, byte [%2]
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imul vald, 0x01010101
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imul vald, 0x01010101
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%if %1 >= 8
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movd m0, vald
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%if mmsize == 16
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pshufd m0, m0, q0000
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%else
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%else
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punpckldq m0, m0
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SPLATB_LOAD m0, %2, m1
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%endif ; mmsize == 16
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%endif ; %1 < 8
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%endif ; %1 > 16
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%endmacro ; READ_V_PIXEL
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%endmacro ; READ_V_PIXEL
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%macro WRITE_V_PIXEL 2
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%macro WRITE_V_PIXEL 2
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@ -388,26 +378,42 @@ VERTICAL_EXTEND 16, 22
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%endif
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%endif
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%endif ; %1-%%off >= 4
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%endif ; %1-%%off >= 4
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%if %1-%%off == 2
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movd [%2+%%off-2], m0
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%endif ; (%1-%%off)/2
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%else ; %1 < 8
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%else ; %1 < 8
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%if cpuflag(mmxext)
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movd [%2+%%off], m0
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%if %1 == 6
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movd [%2+%%off+2], m0
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%endif ; (%1-%%off)/2
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%else ; notcpuflag(mmxext)
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%rep %1/4
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%rep %1/4
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mov [%2+%%off], vald
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mov [%2+%%off], vald
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%assign %%off %%off+4
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%assign %%off %%off+4
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%endrep ; %1/4
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%endrep ; %1/4
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%endif ; %1 >=/< 8
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%if %1-%%off == 2
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%if %1-%%off == 2
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mov [%2+%%off], valw
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mov [%2+%%off], valw
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%endif ; (%1-%%off)/2
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%endif ; (%1-%%off)/2
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%endif ; cpuflag
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%endif ; %1 >=/< 8
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%endmacro ; WRITE_V_PIXEL
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%endmacro ; WRITE_V_PIXEL
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%macro H_EXTEND 2
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%macro H_EXTEND 2
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%assign %%n %1
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%assign %%n %1
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%rep 1+(%2-%1)/2
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%rep 1+(%2-%1)/2
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cglobal emu_edge_hfix %+ %%n, 4, 5, 1, dst, dst_stride, start_x, bh, val
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%if %%n < 8 && notcpuflag(mmxext)
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cglobal emu_edge_hfix %+ %%n, 4, 5, 2, dst, dst_stride, start_x, bh, val
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%else
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cglobal emu_edge_hfix %+ %%n, 4, 4, 2, dst, dst_stride, start_x, bh
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%endif
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.loop_y: ; do {
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.loop_y: ; do {
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READ_V_PIXEL %%n, [dstq+start_xq] ; $variable_regs = read($n)
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READ_V_PIXEL %%n, dstq+start_xq ; $variable_regs = read($n)
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WRITE_V_PIXEL %%n, dstq ; write($variable_regs, $n)
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WRITE_V_PIXEL %%n, dstq ; write($variable_regs, $n)
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add dstq, dst_strideq ; dst += dst_stride
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add dstq, dst_strideq ; dst += dst_stride
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dec bhq ; } while (--bh)
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dec bhq ; } while (--bh)
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@ -418,11 +424,16 @@ cglobal emu_edge_hfix %+ %%n, 4, 5, 1, dst, dst_stride, start_x, bh, val
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%endmacro ; H_EXTEND
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%endmacro ; H_EXTEND
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INIT_MMX mmx
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INIT_MMX mmx
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H_EXTEND 2, 14
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H_EXTEND 2, 2
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%if ARCH_X86_32
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H_EXTEND 4, 22
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%endif
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INIT_MMX mmxext
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H_EXTEND 4, 14
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%if ARCH_X86_32
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%if ARCH_X86_32
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H_EXTEND 16, 22
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H_EXTEND 16, 22
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%endif
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%endif
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INIT_XMM sse2
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INIT_XMM sse2
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H_EXTEND 16, 22
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H_EXTEND 16, 22
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@ -117,15 +117,34 @@ static emu_edge_hfix_func *hfixtbl_mmx[11] = {
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};
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};
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#endif
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#endif
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extern emu_edge_hvar_func ff_emu_edge_hvar_mmx;
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extern emu_edge_hvar_func ff_emu_edge_hvar_mmx;
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extern emu_edge_hfix_func ff_emu_edge_hfix4_mmxext;
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extern emu_edge_hfix_func ff_emu_edge_hfix6_mmxext;
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extern emu_edge_hfix_func ff_emu_edge_hfix8_mmxext;
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extern emu_edge_hfix_func ff_emu_edge_hfix10_mmxext;
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extern emu_edge_hfix_func ff_emu_edge_hfix12_mmxext;
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extern emu_edge_hfix_func ff_emu_edge_hfix14_mmxext;
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extern emu_edge_hfix_func ff_emu_edge_hfix16_mmxext;
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extern emu_edge_hfix_func ff_emu_edge_hfix18_mmxext;
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extern emu_edge_hfix_func ff_emu_edge_hfix20_mmxext;
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extern emu_edge_hfix_func ff_emu_edge_hfix22_mmxext;
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#if ARCH_X86_32
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static emu_edge_hfix_func *hfixtbl_mmxext[11] = {
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ff_emu_edge_hfix2_mmx, ff_emu_edge_hfix4_mmxext, ff_emu_edge_hfix6_mmxext,
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ff_emu_edge_hfix8_mmxext, ff_emu_edge_hfix10_mmxext, ff_emu_edge_hfix12_mmxext,
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ff_emu_edge_hfix14_mmxext, ff_emu_edge_hfix16_mmxext, ff_emu_edge_hfix18_mmxext,
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ff_emu_edge_hfix20_mmxext, ff_emu_edge_hfix22_mmxext
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};
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#endif
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extern emu_edge_hvar_func ff_emu_edge_hvar_mmxext;
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extern emu_edge_hfix_func ff_emu_edge_hfix16_sse2;
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extern emu_edge_hfix_func ff_emu_edge_hfix16_sse2;
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extern emu_edge_hfix_func ff_emu_edge_hfix18_sse2;
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extern emu_edge_hfix_func ff_emu_edge_hfix18_sse2;
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extern emu_edge_hfix_func ff_emu_edge_hfix20_sse2;
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extern emu_edge_hfix_func ff_emu_edge_hfix20_sse2;
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extern emu_edge_hfix_func ff_emu_edge_hfix22_sse2;
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extern emu_edge_hfix_func ff_emu_edge_hfix22_sse2;
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static emu_edge_hfix_func *hfixtbl_sse2[11] = {
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static emu_edge_hfix_func *hfixtbl_sse2[11] = {
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ff_emu_edge_hfix2_mmx, ff_emu_edge_hfix4_mmx, ff_emu_edge_hfix6_mmx,
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ff_emu_edge_hfix2_mmx, ff_emu_edge_hfix4_mmxext, ff_emu_edge_hfix6_mmxext,
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ff_emu_edge_hfix8_mmx, ff_emu_edge_hfix10_mmx, ff_emu_edge_hfix12_mmx,
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ff_emu_edge_hfix8_mmxext, ff_emu_edge_hfix10_mmxext, ff_emu_edge_hfix12_mmxext,
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ff_emu_edge_hfix14_mmx, ff_emu_edge_hfix16_sse2, ff_emu_edge_hfix18_sse2,
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ff_emu_edge_hfix14_mmxext, ff_emu_edge_hfix16_sse2, ff_emu_edge_hfix18_sse2,
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ff_emu_edge_hfix20_sse2, ff_emu_edge_hfix22_sse2
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ff_emu_edge_hfix20_sse2, ff_emu_edge_hfix22_sse2
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};
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};
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extern emu_edge_hvar_func ff_emu_edge_hvar_sse2;
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extern emu_edge_hvar_func ff_emu_edge_hvar_sse2;
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@ -215,6 +234,17 @@ static av_noinline void emulated_edge_mc_mmx(uint8_t *buf, const uint8_t *src,
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hfixtbl_mmx, &ff_emu_edge_hvar_mmx);
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hfixtbl_mmx, &ff_emu_edge_hvar_mmx);
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}
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}
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static av_noinline void emulated_edge_mc_mmxext(uint8_t *buf, const uint8_t *src,
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ptrdiff_t buf_stride,
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ptrdiff_t src_stride,
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int block_w, int block_h,
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int src_x, int src_y, int w, int h)
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{
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emulated_edge_mc(buf, src, buf_stride, src_stride, block_w, block_h,
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src_x, src_y, w, h, vfixtbl_mmx, &ff_emu_edge_vvar_mmx,
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hfixtbl_mmxext, &ff_emu_edge_hvar_mmxext);
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}
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static av_noinline void emulated_edge_mc_sse(uint8_t *buf, const uint8_t *src,
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static av_noinline void emulated_edge_mc_sse(uint8_t *buf, const uint8_t *src,
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ptrdiff_t buf_stride,
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ptrdiff_t buf_stride,
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ptrdiff_t src_stride,
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ptrdiff_t src_stride,
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@ -223,7 +253,7 @@ static av_noinline void emulated_edge_mc_sse(uint8_t *buf, const uint8_t *src,
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{
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{
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emulated_edge_mc(buf, src, buf_stride, src_stride, block_w, block_h,
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emulated_edge_mc(buf, src, buf_stride, src_stride, block_w, block_h,
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src_x, src_y, w, h, vfixtbl_sse, &ff_emu_edge_vvar_sse,
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src_x, src_y, w, h, vfixtbl_sse, &ff_emu_edge_vvar_sse,
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hfixtbl_mmx, &ff_emu_edge_hvar_mmx);
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hfixtbl_mmxext, &ff_emu_edge_hvar_mmxext);
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}
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}
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#endif
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#endif
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@ -258,6 +288,10 @@ av_cold void ff_videodsp_init_x86(VideoDSPContext *ctx, int bpc)
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#endif /* ARCH_X86_32 */
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#endif /* ARCH_X86_32 */
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if (EXTERNAL_MMXEXT(cpu_flags)) {
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if (EXTERNAL_MMXEXT(cpu_flags)) {
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ctx->prefetch = ff_prefetch_mmxext;
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ctx->prefetch = ff_prefetch_mmxext;
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#if ARCH_X86_32
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if (bpc <= 8)
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ctx->emulated_edge_mc = emulated_edge_mc_mmxext;
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#endif /* ARCH_X86_32 */
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}
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}
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#if ARCH_X86_32
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#if ARCH_X86_32
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if (EXTERNAL_SSE(cpu_flags) && bpc <= 8) {
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if (EXTERNAL_SSE(cpu_flags) && bpc <= 8) {
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