2011-12-06 13:44:05 +01:00
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/*
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* Copyright (c) 2008 Mans Rullgard <mans@mansr.com>
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*
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2013-08-15 23:12:51 +02:00
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* This file is part of FFmpeg.
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2011-12-06 13:44:05 +01:00
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*
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2013-08-15 23:12:51 +02:00
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* FFmpeg is free software; you can redistribute it and/or
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2011-12-06 13:44:05 +01:00
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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2013-08-15 23:12:51 +02:00
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* FFmpeg is distributed in the hope that it will be useful,
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2011-12-06 13:44:05 +01:00
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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2013-08-15 23:12:51 +02:00
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* License along with FFmpeg; if not, write to the Free Software
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2011-12-06 13:44:05 +01:00
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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2012-05-21 21:46:23 +02:00
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#include "libavutil/arm/asm.S"
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2011-12-06 13:44:05 +01:00
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/* chroma_mc8(uint8_t *dst, uint8_t *src, int stride, int h, int x, int y) */
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2011-12-05 22:18:05 +01:00
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.macro h264_chroma_mc8 type, codec=h264
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function ff_\type\()_\codec\()_chroma_mc8_neon, export=1
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2011-12-06 13:44:05 +01:00
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push {r4-r7, lr}
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2012-08-01 00:58:58 +02:00
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ldrd r4, r5, [sp, #20]
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2011-12-06 13:44:05 +01:00
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.ifc \type,avg
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mov lr, r0
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.endif
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pld [r1]
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pld [r1, r2]
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2011-12-05 22:18:05 +01:00
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.ifc \codec,rv40
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movrel r6, rv40bias
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lsr r7, r5, #1
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add r6, r6, r7, lsl #3
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lsr r7, r4, #1
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add r6, r6, r7, lsl #1
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vld1.16 {d22[],d23[]}, [r6,:16]
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.endif
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2011-12-06 13:44:05 +01:00
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A muls r7, r4, r5
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T mul r7, r4, r5
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T cmp r7, #0
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rsb r6, r7, r5, lsl #3
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rsb r12, r7, r4, lsl #3
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sub r4, r7, r4, lsl #3
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sub r4, r4, r5, lsl #3
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add r4, r4, #64
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beq 2f
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vdup.8 d0, r4
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vdup.8 d1, r12
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2012-10-19 14:39:11 +02:00
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vld1.8 {d4, d5}, [r1], r2
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2011-12-06 13:44:05 +01:00
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vdup.8 d2, r6
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vdup.8 d3, r7
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vext.8 d5, d4, d5, #1
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2012-10-19 14:39:11 +02:00
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1: vld1.8 {d6, d7}, [r1], r2
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2011-12-06 13:44:05 +01:00
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vmull.u8 q8, d4, d0
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vmlal.u8 q8, d5, d1
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2012-10-19 14:39:11 +02:00
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vext.8 d7, d6, d7, #1
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vld1.8 {d4, d5}, [r1], r2
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2011-12-06 13:44:05 +01:00
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vmlal.u8 q8, d6, d2
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2012-10-19 14:39:11 +02:00
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pld [r1]
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2011-12-06 13:44:05 +01:00
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vext.8 d5, d4, d5, #1
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vmlal.u8 q8, d7, d3
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vmull.u8 q9, d6, d0
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subs r3, r3, #2
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vmlal.u8 q9, d7, d1
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vmlal.u8 q9, d4, d2
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vmlal.u8 q9, d5, d3
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2012-10-19 14:39:11 +02:00
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pld [r1, r2]
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2011-12-05 22:18:05 +01:00
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.ifc \codec,h264
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vrshrn.u16 d16, q8, #6
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2011-12-06 13:44:05 +01:00
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vrshrn.u16 d17, q9, #6
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2011-12-05 22:18:05 +01:00
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.else
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vadd.u16 q8, q8, q11
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vadd.u16 q9, q9, q11
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vshrn.u16 d16, q8, #6
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vshrn.u16 d17, q9, #6
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.endif
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2011-12-06 13:44:05 +01:00
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.ifc \type,avg
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vld1.8 {d20}, [lr,:64], r2
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vld1.8 {d21}, [lr,:64], r2
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vrhadd.u8 q8, q8, q10
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.endif
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vst1.8 {d16}, [r0,:64], r2
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vst1.8 {d17}, [r0,:64], r2
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bgt 1b
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pop {r4-r7, pc}
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2: tst r6, r6
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add r12, r12, r6
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vdup.8 d0, r4
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vdup.8 d1, r12
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beq 4f
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2012-10-19 14:39:11 +02:00
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vld1.8 {d4}, [r1], r2
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2011-12-06 13:44:05 +01:00
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2012-10-19 14:39:11 +02:00
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3: vld1.8 {d6}, [r1], r2
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2011-12-06 13:44:05 +01:00
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vmull.u8 q8, d4, d0
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vmlal.u8 q8, d6, d1
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2012-10-19 14:39:11 +02:00
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vld1.8 {d4}, [r1], r2
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2011-12-06 13:44:05 +01:00
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vmull.u8 q9, d6, d0
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vmlal.u8 q9, d4, d1
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2012-10-19 14:39:11 +02:00
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pld [r1]
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2011-12-05 22:18:05 +01:00
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.ifc \codec,h264
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2011-12-06 13:44:05 +01:00
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vrshrn.u16 d16, q8, #6
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vrshrn.u16 d17, q9, #6
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2011-12-05 22:18:05 +01:00
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.else
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vadd.u16 q8, q8, q11
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vadd.u16 q9, q9, q11
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vshrn.u16 d16, q8, #6
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vshrn.u16 d17, q9, #6
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.endif
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2012-10-19 14:39:11 +02:00
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pld [r1, r2]
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2011-12-06 13:44:05 +01:00
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.ifc \type,avg
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vld1.8 {d20}, [lr,:64], r2
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vld1.8 {d21}, [lr,:64], r2
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vrhadd.u8 q8, q8, q10
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.endif
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subs r3, r3, #2
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vst1.8 {d16}, [r0,:64], r2
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vst1.8 {d17}, [r0,:64], r2
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bgt 3b
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pop {r4-r7, pc}
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4: vld1.8 {d4, d5}, [r1], r2
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vld1.8 {d6, d7}, [r1], r2
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vext.8 d5, d4, d5, #1
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vext.8 d7, d6, d7, #1
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2012-10-19 14:39:11 +02:00
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pld [r1]
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2011-12-06 13:44:05 +01:00
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subs r3, r3, #2
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vmull.u8 q8, d4, d0
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vmlal.u8 q8, d5, d1
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vmull.u8 q9, d6, d0
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vmlal.u8 q9, d7, d1
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2012-10-19 14:39:11 +02:00
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pld [r1, r2]
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2011-12-05 22:18:05 +01:00
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.ifc \codec,h264
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2011-12-06 13:44:05 +01:00
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vrshrn.u16 d16, q8, #6
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vrshrn.u16 d17, q9, #6
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2011-12-05 22:18:05 +01:00
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.else
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vadd.u16 q8, q8, q11
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vadd.u16 q9, q9, q11
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vshrn.u16 d16, q8, #6
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vshrn.u16 d17, q9, #6
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.endif
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2011-12-06 13:44:05 +01:00
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.ifc \type,avg
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vld1.8 {d20}, [lr,:64], r2
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vld1.8 {d21}, [lr,:64], r2
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vrhadd.u8 q8, q8, q10
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.endif
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vst1.8 {d16}, [r0,:64], r2
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vst1.8 {d17}, [r0,:64], r2
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2012-10-19 14:39:11 +02:00
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bgt 4b
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2011-12-06 13:44:05 +01:00
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pop {r4-r7, pc}
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endfunc
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.endm
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/* chroma_mc4(uint8_t *dst, uint8_t *src, int stride, int h, int x, int y) */
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2011-12-05 22:18:05 +01:00
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.macro h264_chroma_mc4 type, codec=h264
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function ff_\type\()_\codec\()_chroma_mc4_neon, export=1
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2011-12-06 13:44:05 +01:00
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push {r4-r7, lr}
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2012-08-01 00:58:58 +02:00
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ldrd r4, r5, [sp, #20]
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2011-12-06 13:44:05 +01:00
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.ifc \type,avg
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mov lr, r0
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.endif
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pld [r1]
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pld [r1, r2]
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2011-12-05 22:18:05 +01:00
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.ifc \codec,rv40
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movrel r6, rv40bias
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lsr r7, r5, #1
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add r6, r6, r7, lsl #3
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lsr r7, r4, #1
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add r6, r6, r7, lsl #1
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vld1.16 {d22[],d23[]}, [r6,:16]
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.endif
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2011-12-06 13:44:05 +01:00
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A muls r7, r4, r5
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T mul r7, r4, r5
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T cmp r7, #0
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rsb r6, r7, r5, lsl #3
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rsb r12, r7, r4, lsl #3
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sub r4, r7, r4, lsl #3
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sub r4, r4, r5, lsl #3
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add r4, r4, #64
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beq 2f
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vdup.8 d0, r4
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vdup.8 d1, r12
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2012-10-19 14:39:11 +02:00
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vld1.8 {d4}, [r1], r2
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2011-12-06 13:44:05 +01:00
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vdup.8 d2, r6
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vdup.8 d3, r7
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vext.8 d5, d4, d5, #1
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vtrn.32 d4, d5
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vtrn.32 d0, d1
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vtrn.32 d2, d3
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2012-10-19 14:39:11 +02:00
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1: vld1.8 {d6}, [r1], r2
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vext.8 d7, d6, d7, #1
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vtrn.32 d6, d7
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2011-12-06 13:44:05 +01:00
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vmull.u8 q8, d4, d0
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vmlal.u8 q8, d6, d2
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2012-10-19 14:39:11 +02:00
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vld1.8 {d4}, [r1], r2
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2011-12-06 13:44:05 +01:00
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vext.8 d5, d4, d5, #1
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vtrn.32 d4, d5
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2012-10-19 14:39:11 +02:00
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pld [r1]
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2011-12-06 13:44:05 +01:00
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vmull.u8 q9, d6, d0
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vmlal.u8 q9, d4, d2
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vadd.i16 d16, d16, d17
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vadd.i16 d17, d18, d19
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2011-12-05 22:18:05 +01:00
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.ifc \codec,h264
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2011-12-06 13:44:05 +01:00
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vrshrn.u16 d16, q8, #6
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2011-12-05 22:18:05 +01:00
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.else
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vadd.u16 q8, q8, q11
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vshrn.u16 d16, q8, #6
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.endif
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2011-12-06 13:44:05 +01:00
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subs r3, r3, #2
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2012-10-19 14:39:11 +02:00
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pld [r1, r2]
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2011-12-06 13:44:05 +01:00
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.ifc \type,avg
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vld1.32 {d20[0]}, [lr,:32], r2
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vld1.32 {d20[1]}, [lr,:32], r2
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vrhadd.u8 d16, d16, d20
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.endif
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vst1.32 {d16[0]}, [r0,:32], r2
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vst1.32 {d16[1]}, [r0,:32], r2
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bgt 1b
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pop {r4-r7, pc}
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2: tst r6, r6
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add r12, r12, r6
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vdup.8 d0, r4
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vdup.8 d1, r12
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vtrn.32 d0, d1
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beq 4f
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vext.32 d1, d0, d1, #1
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2012-10-19 14:39:11 +02:00
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vld1.32 {d4[0]}, [r1], r2
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2011-12-06 13:44:05 +01:00
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2012-10-19 14:39:11 +02:00
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3: vld1.32 {d4[1]}, [r1], r2
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2011-12-06 13:44:05 +01:00
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vmull.u8 q8, d4, d0
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2012-10-19 14:39:11 +02:00
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vld1.32 {d4[0]}, [r1], r2
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2011-12-06 13:44:05 +01:00
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vmull.u8 q9, d4, d1
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vadd.i16 d16, d16, d17
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vadd.i16 d17, d18, d19
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2012-10-19 14:39:11 +02:00
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pld [r1]
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2011-12-05 22:18:05 +01:00
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.ifc \codec,h264
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2011-12-06 13:44:05 +01:00
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vrshrn.u16 d16, q8, #6
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2011-12-05 22:18:05 +01:00
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.else
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vadd.u16 q8, q8, q11
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|
vshrn.u16 d16, q8, #6
|
|
|
|
|
.endif
|
2011-12-06 13:44:05 +01:00
|
|
|
.ifc \type,avg
|
|
|
|
|
vld1.32 {d20[0]}, [lr,:32], r2
|
|
|
|
|
vld1.32 {d20[1]}, [lr,:32], r2
|
|
|
|
|
vrhadd.u8 d16, d16, d20
|
|
|
|
|
.endif
|
|
|
|
|
subs r3, r3, #2
|
2012-10-19 14:39:11 +02:00
|
|
|
pld [r1, r2]
|
2011-12-06 13:44:05 +01:00
|
|
|
vst1.32 {d16[0]}, [r0,:32], r2
|
|
|
|
|
vst1.32 {d16[1]}, [r0,:32], r2
|
|
|
|
|
bgt 3b
|
|
|
|
|
|
|
|
|
|
pop {r4-r7, pc}
|
|
|
|
|
|
|
|
|
|
4: vld1.8 {d4}, [r1], r2
|
|
|
|
|
vld1.8 {d6}, [r1], r2
|
|
|
|
|
vext.8 d5, d4, d5, #1
|
|
|
|
|
vext.8 d7, d6, d7, #1
|
|
|
|
|
vtrn.32 d4, d5
|
|
|
|
|
vtrn.32 d6, d7
|
2012-10-19 14:39:11 +02:00
|
|
|
vmull.u8 q8, d4, d0
|
2011-12-06 13:44:05 +01:00
|
|
|
vmull.u8 q9, d6, d0
|
|
|
|
|
subs r3, r3, #2
|
|
|
|
|
vadd.i16 d16, d16, d17
|
|
|
|
|
vadd.i16 d17, d18, d19
|
|
|
|
|
pld [r1]
|
2011-12-05 22:18:05 +01:00
|
|
|
.ifc \codec,h264
|
2011-12-06 13:44:05 +01:00
|
|
|
vrshrn.u16 d16, q8, #6
|
2011-12-05 22:18:05 +01:00
|
|
|
.else
|
|
|
|
|
vadd.u16 q8, q8, q11
|
|
|
|
|
vshrn.u16 d16, q8, #6
|
|
|
|
|
.endif
|
2011-12-06 13:44:05 +01:00
|
|
|
.ifc \type,avg
|
|
|
|
|
vld1.32 {d20[0]}, [lr,:32], r2
|
|
|
|
|
vld1.32 {d20[1]}, [lr,:32], r2
|
|
|
|
|
vrhadd.u8 d16, d16, d20
|
|
|
|
|
.endif
|
|
|
|
|
pld [r1]
|
|
|
|
|
vst1.32 {d16[0]}, [r0,:32], r2
|
|
|
|
|
vst1.32 {d16[1]}, [r0,:32], r2
|
2012-10-19 14:39:11 +02:00
|
|
|
bgt 4b
|
2011-12-06 13:44:05 +01:00
|
|
|
|
|
|
|
|
pop {r4-r7, pc}
|
|
|
|
|
endfunc
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
.macro h264_chroma_mc2 type
|
|
|
|
|
function ff_\type\()_h264_chroma_mc2_neon, export=1
|
|
|
|
|
push {r4-r6, lr}
|
|
|
|
|
ldr r4, [sp, #16]
|
|
|
|
|
ldr lr, [sp, #20]
|
|
|
|
|
pld [r1]
|
|
|
|
|
pld [r1, r2]
|
|
|
|
|
orrs r5, r4, lr
|
|
|
|
|
beq 2f
|
|
|
|
|
|
|
|
|
|
mul r5, r4, lr
|
|
|
|
|
rsb r6, r5, lr, lsl #3
|
|
|
|
|
rsb r12, r5, r4, lsl #3
|
|
|
|
|
sub r4, r5, r4, lsl #3
|
|
|
|
|
sub r4, r4, lr, lsl #3
|
|
|
|
|
add r4, r4, #64
|
|
|
|
|
vdup.8 d0, r4
|
|
|
|
|
vdup.8 d2, r12
|
|
|
|
|
vdup.8 d1, r6
|
|
|
|
|
vdup.8 d3, r5
|
|
|
|
|
vtrn.16 q0, q1
|
|
|
|
|
1:
|
|
|
|
|
vld1.32 {d4[0]}, [r1], r2
|
|
|
|
|
vld1.32 {d4[1]}, [r1], r2
|
|
|
|
|
vrev64.32 d5, d4
|
|
|
|
|
vld1.32 {d5[1]}, [r1]
|
|
|
|
|
vext.8 q3, q2, q2, #1
|
|
|
|
|
vtrn.16 q2, q3
|
|
|
|
|
vmull.u8 q8, d4, d0
|
|
|
|
|
vmlal.u8 q8, d5, d1
|
|
|
|
|
.ifc \type,avg
|
|
|
|
|
vld1.16 {d18[0]}, [r0,:16], r2
|
|
|
|
|
vld1.16 {d18[1]}, [r0,:16]
|
|
|
|
|
sub r0, r0, r2
|
|
|
|
|
.endif
|
|
|
|
|
vtrn.32 d16, d17
|
|
|
|
|
vadd.i16 d16, d16, d17
|
|
|
|
|
vrshrn.u16 d16, q8, #6
|
|
|
|
|
.ifc \type,avg
|
|
|
|
|
vrhadd.u8 d16, d16, d18
|
|
|
|
|
.endif
|
|
|
|
|
vst1.16 {d16[0]}, [r0,:16], r2
|
|
|
|
|
vst1.16 {d16[1]}, [r0,:16], r2
|
|
|
|
|
subs r3, r3, #2
|
|
|
|
|
bgt 1b
|
|
|
|
|
pop {r4-r6, pc}
|
|
|
|
|
2:
|
|
|
|
|
.ifc \type,put
|
|
|
|
|
ldrh_post r5, r1, r2
|
|
|
|
|
strh_post r5, r0, r2
|
|
|
|
|
ldrh_post r6, r1, r2
|
|
|
|
|
strh_post r6, r0, r2
|
|
|
|
|
.else
|
|
|
|
|
vld1.16 {d16[0]}, [r1], r2
|
|
|
|
|
vld1.16 {d16[1]}, [r1], r2
|
|
|
|
|
vld1.16 {d18[0]}, [r0,:16], r2
|
|
|
|
|
vld1.16 {d18[1]}, [r0,:16]
|
|
|
|
|
sub r0, r0, r2
|
|
|
|
|
vrhadd.u8 d16, d16, d18
|
|
|
|
|
vst1.16 {d16[0]}, [r0,:16], r2
|
|
|
|
|
vst1.16 {d16[1]}, [r0,:16], r2
|
|
|
|
|
.endif
|
|
|
|
|
subs r3, r3, #2
|
|
|
|
|
bgt 2b
|
|
|
|
|
pop {r4-r6, pc}
|
|
|
|
|
endfunc
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
h264_chroma_mc8 put
|
|
|
|
|
h264_chroma_mc8 avg
|
|
|
|
|
h264_chroma_mc4 put
|
|
|
|
|
h264_chroma_mc4 avg
|
|
|
|
|
h264_chroma_mc2 put
|
|
|
|
|
h264_chroma_mc2 avg
|
2011-12-05 22:18:05 +01:00
|
|
|
|
|
|
|
|
#if CONFIG_RV40_DECODER
|
|
|
|
|
const rv40bias
|
|
|
|
|
.short 0, 16, 32, 16
|
|
|
|
|
.short 32, 28, 32, 28
|
|
|
|
|
.short 0, 32, 16, 32
|
|
|
|
|
.short 32, 28, 32, 28
|
|
|
|
|
endconst
|
|
|
|
|
|
|
|
|
|
h264_chroma_mc8 put, rv40
|
|
|
|
|
h264_chroma_mc8 avg, rv40
|
|
|
|
|
h264_chroma_mc4 put, rv40
|
|
|
|
|
h264_chroma_mc4 avg, rv40
|
|
|
|
|
#endif
|
