2014-01-07 12:23:13 +01:00
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;******************************************************************************
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;* SIMD-optimized HuffYUV functions
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;* Copyright (c) 2008 Loren Merritt
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2014-05-28 21:57:38 +02:00
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;* Copyright (c) 2014 Christophe Gisquet
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2014-01-07 12:23:13 +01:00
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;*
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2014-05-27 23:07:36 +02:00
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;* This file is part of FFmpeg.
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2014-01-07 12:23:13 +01:00
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;*
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2014-05-27 23:07:36 +02:00
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;* FFmpeg is free software; you can redistribute it and/or
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2014-01-07 12:23:13 +01:00
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;* modify it under the terms of the GNU Lesser General Public
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;* License as published by the Free Software Foundation; either
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;* version 2.1 of the License, or (at your option) any later version.
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;*
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2014-05-27 23:07:36 +02:00
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;* FFmpeg is distributed in the hope that it will be useful,
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2014-01-07 12:23:13 +01:00
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;* but WITHOUT ANY WARRANTY; without even the implied warranty of
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;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;* Lesser General Public License for more details.
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;*
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;* You should have received a copy of the GNU Lesser General Public
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2014-05-27 23:07:36 +02:00
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;* License along with FFmpeg; if not, write to the Free Software
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2014-01-07 12:23:13 +01:00
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;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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;******************************************************************************
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%include "libavutil/x86/x86util.asm"
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SECTION_RODATA
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2015-02-05 20:20:43 +01:00
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cextern pb_15
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2014-01-07 12:23:13 +01:00
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pb_zzzzzzzz77777777: times 8 db -1
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pb_7: times 8 db 7
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pb_zzzz3333zzzzbbbb: db -1,-1,-1,-1,3,3,3,3,-1,-1,-1,-1,11,11,11,11
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pb_zz11zz55zz99zzdd: db -1,-1,1,1,-1,-1,5,5,-1,-1,9,9,-1,-1,13,13
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SECTION_TEXT
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; void ff_add_hfyu_median_pred_mmxext(uint8_t *dst, const uint8_t *top,
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; const uint8_t *diff, int w,
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; int *left, int *left_top)
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2014-05-28 01:03:23 +02:00
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%macro HFYU_MEDIAN 0
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cglobal add_hfyu_median_pred, 6,6,8, dst, top, diff, w, left, left_top
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movu m0, [topq]
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mova m2, m0
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movd m4, [left_topq]
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LSHIFT m2, 1
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mova m1, m0
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por m4, m2
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movd m3, [leftq]
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psubb m0, m4 ; t-tl
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2014-01-07 12:23:13 +01:00
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add dstq, wq
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add topq, wq
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add diffq, wq
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neg wq
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jmp .skip
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.loop:
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2014-05-28 01:03:23 +02:00
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movu m4, [topq+wq]
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mova m0, m4
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LSHIFT m4, 1
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por m4, m1
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mova m1, m0 ; t
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psubb m0, m4 ; t-tl
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2014-01-07 12:23:13 +01:00
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.skip:
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2014-05-28 01:03:23 +02:00
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movu m2, [diffq+wq]
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2014-01-07 12:23:13 +01:00
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%assign i 0
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2014-05-28 01:03:23 +02:00
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%rep mmsize
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mova m4, m0
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paddb m4, m3 ; t-tl+l
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mova m5, m3
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pmaxub m3, m1
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pminub m5, m1
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pminub m3, m4
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pmaxub m3, m5 ; median
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paddb m3, m2 ; +residual
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2014-01-07 12:23:13 +01:00
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%if i==0
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2014-05-28 01:03:23 +02:00
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mova m7, m3
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LSHIFT m7, mmsize-1
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2014-01-07 12:23:13 +01:00
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%else
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2014-05-28 01:03:23 +02:00
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mova m6, m3
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RSHIFT m7, 1
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LSHIFT m6, mmsize-1
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por m7, m6
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2014-01-07 12:23:13 +01:00
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%endif
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2014-05-28 01:03:23 +02:00
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%if i<mmsize-1
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RSHIFT m0, 1
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RSHIFT m1, 1
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RSHIFT m2, 1
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2014-01-07 12:23:13 +01:00
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%endif
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%assign i i+1
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%endrep
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2014-05-28 01:03:23 +02:00
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movu [dstq+wq], m7
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add wq, mmsize
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2014-01-07 12:23:13 +01:00
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jl .loop
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movzx r2d, byte [dstq-1]
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mov [leftq], r2d
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movzx r2d, byte [topq-1]
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mov [left_topq], r2d
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RET
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2014-05-28 01:03:23 +02:00
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%endmacro
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2014-05-30 11:57:56 +02:00
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%if ARCH_X86_32
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2014-05-28 01:03:23 +02:00
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INIT_MMX mmxext
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HFYU_MEDIAN
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2014-05-30 11:57:56 +02:00
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%endif
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2014-05-28 01:03:23 +02:00
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INIT_XMM sse2
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HFYU_MEDIAN
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2014-01-07 12:23:13 +01:00
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%macro ADD_HFYU_LEFT_LOOP 2 ; %1 = dst_is_aligned, %2 = src_is_aligned
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add srcq, wq
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add dstq, wq
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neg wq
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%%.loop:
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%if %2
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mova m1, [srcq+wq]
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%else
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movu m1, [srcq+wq]
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%endif
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mova m2, m1
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psllw m1, 8
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paddb m1, m2
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mova m2, m1
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pshufb m1, m3
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paddb m1, m2
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pshufb m0, m5
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mova m2, m1
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pshufb m1, m4
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paddb m1, m2
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%if mmsize == 16
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mova m2, m1
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pshufb m1, m6
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paddb m1, m2
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%endif
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paddb m0, m1
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%if %1
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mova [dstq+wq], m0
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%else
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movq [dstq+wq], m0
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movhps [dstq+wq+8], m0
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%endif
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add wq, mmsize
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jl %%.loop
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mov eax, mmsize-1
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sub eax, wd
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movd m1, eax
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pshufb m0, m1
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movd eax, m0
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RET
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%endmacro
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; int ff_add_hfyu_left_pred(uint8_t *dst, const uint8_t *src, int w, int left)
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INIT_MMX ssse3
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cglobal add_hfyu_left_pred, 3,3,7, dst, src, w, left
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.skip_prologue:
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mova m5, [pb_7]
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mova m4, [pb_zzzz3333zzzzbbbb]
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mova m3, [pb_zz11zz55zz99zzdd]
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movd m0, leftm
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psllq m0, 56
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ADD_HFYU_LEFT_LOOP 1, 1
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INIT_XMM sse4
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cglobal add_hfyu_left_pred, 3,3,7, dst, src, w, left
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2015-02-05 20:20:43 +01:00
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mova m5, [pb_15]
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2014-01-07 12:23:13 +01:00
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mova m6, [pb_zzzzzzzz77777777]
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mova m4, [pb_zzzz3333zzzzbbbb]
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mova m3, [pb_zz11zz55zz99zzdd]
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movd m0, leftm
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pslldq m0, 15
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test srcq, 15
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jnz .src_unaligned
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test dstq, 15
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jnz .dst_unaligned
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ADD_HFYU_LEFT_LOOP 1, 1
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.dst_unaligned:
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ADD_HFYU_LEFT_LOOP 0, 1
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.src_unaligned:
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ADD_HFYU_LEFT_LOOP 0, 0
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2014-05-28 15:52:24 +02:00
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%macro ADD_BYTES 0
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cglobal add_bytes, 3,4,2, dst, src, w, size
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mov sizeq, wq
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and sizeq, -2*mmsize
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jz .2
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add dstq, sizeq
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add srcq, sizeq
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neg sizeq
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.1:
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mova m0, [srcq + sizeq]
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mova m1, [srcq + sizeq + mmsize]
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paddb m0, [dstq + sizeq]
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paddb m1, [dstq + sizeq + mmsize]
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mova [dstq + sizeq], m0
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mova [dstq + sizeq + mmsize], m1
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add sizeq, 2*mmsize
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jl .1
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.2:
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and wq, 2*mmsize-1
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jz .end
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add dstq, wq
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add srcq, wq
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neg wq
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2015-07-26 07:28:16 +02:00
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.3:
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2014-05-28 15:52:24 +02:00
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mov sizeb, [srcq + wq]
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add [dstq + wq], sizeb
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inc wq
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jl .3
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.end:
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REP_RET
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%endmacro
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2014-05-30 11:57:56 +02:00
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%if ARCH_X86_32
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2014-05-28 15:52:24 +02:00
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INIT_MMX mmx
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ADD_BYTES
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2014-05-30 11:57:56 +02:00
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%endif
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2014-05-28 15:52:24 +02:00
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INIT_XMM sse2
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ADD_BYTES
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2014-05-28 21:57:38 +02:00
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; void add_hfyu_left_pred_bgr32(uint8_t *dst, const uint8_t *src,
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; intptr_t w, uint8_t *left)
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%macro LEFT_BGR32 0
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cglobal add_hfyu_left_pred_bgr32, 4,4,3, dst, src, w, left
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shl wq, 2
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movd m0, [leftq]
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lea dstq, [dstq + wq]
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lea srcq, [srcq + wq]
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LSHIFT m0, mmsize-4
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neg wq
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.loop:
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movu m1, [srcq+wq]
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mova m2, m1
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%if mmsize == 8
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punpckhdq m0, m0
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%endif
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LSHIFT m1, 4
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paddb m1, m2
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%if mmsize == 16
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pshufd m0, m0, q3333
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mova m2, m1
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LSHIFT m1, 8
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paddb m1, m2
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%endif
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paddb m0, m1
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movu [dstq+wq], m0
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add wq, mmsize
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jl .loop
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movd m0, [dstq-4]
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movd [leftq], m0
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REP_RET
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%endmacro
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2014-05-30 11:57:56 +02:00
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%if ARCH_X86_32
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2014-05-28 21:57:38 +02:00
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INIT_MMX mmx
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LEFT_BGR32
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2014-05-30 11:57:56 +02:00
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%endif
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2014-05-28 21:57:38 +02:00
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INIT_XMM sse2
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LEFT_BGR32
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