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A compiler writer's guide to <atomic>, minor update

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git-svn-id: https://llvm.org/svn/llvm-project/libcxx/trunk@115633 91177308-0d34-0410-b5e6-96231b3b80d8
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Howard Hinnant 2010-10-05 17:22:28 +00:00
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@ -377,11 +377,17 @@ for the detailed definitions of each of these orderings).
<p> <p>
On some platforms, the compiler vendor can offer some or even all of the above On some platforms, the compiler vendor can offer some or even all of the above
intrinsics at one or more weaker levels of memory synchronization. This might intrinsics at one or more weaker levels of memory synchronization. This might
lead for example to not issuing an <tt>mfense</tt> instruction on the x86. If lead for example to not issuing an <tt>mfense</tt> instruction on the x86.
the compiler does not offer any given operation, at any given memory ordering </p>
<p>
If the compiler does not offer any given operation, at any given memory ordering
level, the library will automatically attempt to call the next highest memory level, the library will automatically attempt to call the next highest memory
ordering operation. This continues up to <tt>seq_cst</tt>, and if that doesn't ordering operation. This continues up to <tt>seq_cst</tt>, and if that doesn't
exist, then the library takes over and does the job with a <tt>mutex</tt>. exist, then the library takes over and does the job with a <tt>mutex</tt>. This
is a compile-time search &amp; selection operation. At run time, the
application will only see the few inlined assembly instructions for the selected
intrinsic.
</p> </p>
<p> <p>