generic-library/bionic
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity
fed22f73c1
bionic/libc/arch-mips64/bionic
History
Duane Sand dd37251c47 [MIPSR6] setjmp supports mips32r6 and FP64A/FPXX reg models 
Save and restore floating point registers via 64-bit
load/stores when possible.  Use assembler's builtin macro
ops to generate pairs of 32-bit load/stores on Mips I cpus.

Some cpus or FR modes have only 16 even-numbered dp fp regs.
This is exposed by _MIPS_FPSET, defined by existing compilers.

Change-Id: I7f617a3ffea8da41c402ef3a68ab32c91d3d7622
2014-07-23 13:57:30 -07:00
..
__bionic_clone.S Rename __bionic_clone_entry to __start_thread. 2014-06-06 15:18:54 -07:00
__get_sp.S Hide __get_sp. 2014-05-20 20:22:50 -07:00
_exit_with_stack_teardown.S Hide _exit_with_stack_teardown. 2014-05-16 16:17:44 -07:00
_setjmp.S [MIPSR6] setjmp supports mips32r6 and FP64A/FPXX reg models 2014-07-23 13:57:30 -07:00
atexit.h [MIPS64] libc/libm support 2014-02-06 16:22:20 -08:00
crtbegin_so.c [MIPS64] libc/libm support 2014-02-06 16:22:20 -08:00
crtbegin.c [MIPS64] libc/libm support 2014-02-06 16:22:20 -08:00
setjmp.S [MIPSR6] setjmp supports mips32r6 and FP64A/FPXX reg models 2014-07-23 13:57:30 -07:00
sigsetjmp.S Unify our assembler macros. 2014-02-20 13:51:26 -08:00
syscall.S Unify our assembler macros. 2014-02-20 13:51:26 -08:00