e31bfae2ba
We're going to modify the __atomic_xxx implementation to provide
full memory barriers, to avoid problems for NDK machine code that
link to these functions.
First step is to remove their usage from our platform code.
We now use inlined versions of the same functions for a slight
performance boost.
+ remove obsolete atomics_x86.c (was never compiled)
NOTE: This improvement was benchmarked on various devices.
Comparing a pthread mutex lock + atomic increment + unlock
we get:
- ARMv7 emulator, running on a 2.4 GHz Xeon:
before: 396 ns after: 288 ns
- x86 emulator in KVM mode on same machine:
before: 27 ns after: 27 ns
- Google Nexus S, in ARMv7 mode (single-core):
before: 82 ns after: 76 ns
- Motorola Xoom, in ARMv7 mode (multi-core):
before: 121 ns after: 120 ns
The code has also been rebuilt in ARMv5TE mode for correctness.
Change-Id: Ic1dc72b173d59b2e7af901dd70d6a72fb2f64b17
285 lines
8.9 KiB
C
285 lines
8.9 KiB
C
/*
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* Copyright (C) 2011 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef BIONIC_ATOMIC_ARM_H
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#define BIONIC_ATOMIC_ARM_H
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#include <machine/cpu-features.h>
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/* Some of the harware instructions used below are not available in Thumb-1
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* mode (they are if you build in ARM or Thumb-2 mode though). To solve this
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* problem, we're going to use the same technique than libatomics_ops,
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* which is to temporarily switch to ARM, do the operation, then switch
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* back to Thumb-1.
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*
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* This results in two 'bx' jumps, just like a normal function call, but
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* everything is kept inlined, avoids loading or computing the function's
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* address, and prevents a little I-cache trashing too.
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*
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* However, it is highly recommended to avoid compiling any C library source
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* file that use these functions in Thumb-1 mode.
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*
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* Define three helper macros to implement this:
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*/
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#if defined(__thumb__) && !defined(__thumb2__)
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# define __ATOMIC_SWITCH_TO_ARM \
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"adr r3, 5f\n" \
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"bx r3\n" \
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".align\n" \
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".arm\n" \
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"5:\n"
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/* note: the leading \n below is intentional */
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# define __ATOMIC_SWITCH_TO_THUMB \
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"\n" \
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"adr r3, 6f\n" \
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"bx r3\n" \
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".thumb" \
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"6:\n"
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# define __ATOMIC_CLOBBERS "r3" /* list of clobbered registers */
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/* Warn the user that ARM mode should really be preferred! */
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# warning Rebuilding this source file in ARM mode is highly recommended for performance!!
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#else
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# define __ATOMIC_SWITCH_TO_ARM /* nothing */
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# define __ATOMIC_SWITCH_TO_THUMB /* nothing */
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# define __ATOMIC_CLOBBERS /* nothing */
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#endif
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/* Define a full memory barrier, this is only needed if we build the
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* platform for a multi-core device. For the record, using a 'dmb'
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* instruction on a Nexus One device can take up to 180 ns even if
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* it is completely un-necessary on this device.
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*
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* NOTE: This is where the platform and NDK headers atomic headers are
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* going to diverge. With the NDK, we don't know if the generated
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* code is going to run on a single or multi-core device, so we
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* need to be cautious.
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*
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* Fortunately, we can use the kernel helper function that is
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* mapped at address 0xffff0fa0 in all user process, and that
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* provides a device-specific barrier operation.
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*
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* I.e. on single-core devices, the helper immediately returns,
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* on multi-core devices, it uses "dmb" or any other means to
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* perform a full-memory barrier.
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*
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* There are three cases to consider for the platform:
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*
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* - multi-core ARMv7-A => use the 'dmb' hardware instruction
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* - multi-core ARMv6 => use the coprocessor
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* - single core ARMv5TE/6/7 => do not use any hardware barrier
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*/
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#if defined(ANDROID_SMP) && ANDROID_SMP == 1
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/* Sanity check, multi-core is only supported starting from ARMv6 */
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# if __ARM_ARCH__ < 6
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# error ANDROID_SMP should not be set to 1 for an ARM architecture less than 6
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# endif
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# ifdef __ARM_HAVE_DMB
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/* For ARMv7-A, we can use the 'dmb' instruction directly */
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__ATOMIC_INLINE__ void
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__bionic_memory_barrier(void)
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{
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/* Note: we always build in ARM or Thumb-2 on ARMv7-A, so don't
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* bother with __ATOMIC_SWITCH_TO_ARM */
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__asm__ __volatile__ ( "dmb" : : : "memory" );
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}
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# else /* !__ARM_HAVE_DMB */
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/* Otherwise, i.e. for multi-core ARMv6, we need to use the coprocessor,
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* which requires the use of a general-purpose register, which is slightly
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* less efficient.
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*/
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__ATOMIC_INLINE__ void
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__bionic_memory_barrier(void)
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{
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__asm__ __volatile__ (
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__SWITCH_TO_ARM
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"mcr p15, 0, %0, c7, c10, 5"
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__SWITCH_TO_THUMB
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: : "r" (0) : __ATOMIC_CLOBBERS "memory");
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}
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# endif /* !__ARM_HAVE_DMB */
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#else /* !ANDROID_SMP */
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__ATOMIC_INLINE__ void
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__bionic_memory_barrier(void)
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{
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/* A simple compiler barrier */
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__asm__ __volatile__ ( "" : : : "memory" );
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}
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#endif /* !ANDROID_SMP */
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/* Compare-and-swap, without any explicit barriers. Note that this functions
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* returns 0 on success, and 1 on failure. The opposite convention is typically
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* used on other platforms.
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*
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* There are two cases to consider:
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*
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* - ARMv6+ => use LDREX/STREX instructions
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* - < ARMv6 => use kernel helper function mapped at 0xffff0fc0
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*
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* LDREX/STREX are only available starting from ARMv6
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*/
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#ifdef __ARM_HAVE_LDREX_STREX
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__ATOMIC_INLINE__ int
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__bionic_cmpxchg(int32_t old_value, int32_t new_value, volatile int32_t* ptr)
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{
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int32_t prev, status;
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do {
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__asm__ __volatile__ (
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__ATOMIC_SWITCH_TO_ARM
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"ldrex %0, [%3]\n"
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"mov %1, #0\n"
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"teq %0, %4\n"
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#ifdef __thumb2__
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"it eq\n"
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#endif
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"strexeq %1, %5, [%3]"
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__ATOMIC_SWITCH_TO_THUMB
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: "=&r" (prev), "=&r" (status), "+m"(*ptr)
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: "r" (ptr), "Ir" (old_value), "r" (new_value)
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: __ATOMIC_CLOBBERS "cc");
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} while (__builtin_expect(status != 0, 0));
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return prev != old_value;
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}
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# else /* !__ARM_HAVE_LDREX_STREX */
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/* Use the handy kernel helper function mapped at 0xffff0fc0 */
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typedef int (kernel_cmpxchg)(int32_t, int32_t, volatile int32_t *);
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__ATOMIC_INLINE__ int
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__kernel_cmpxchg(int32_t old_value, int32_t new_value, volatile int32_t* ptr)
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{
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/* Note: the kernel function returns 0 on success too */
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return (*(kernel_cmpxchg *)0xffff0fc0)(old_value, new_value, ptr);
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}
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__ATOMIC_INLINE__ int
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__bionic_cmpxchg(int32_t old_value, int32_t new_value, volatile int32_t* ptr)
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{
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return __kernel_cmpxchg(old_value, new_value, ptr);
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}
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#endif /* !__ARM_HAVE_LDREX_STREX */
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/* Swap operation, without any explicit barriers.
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* There are again two similar cases to consider:
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*
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* ARMv6+ => use LDREX/STREX
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* < ARMv6 => use SWP instead.
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*/
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#ifdef __ARM_HAVE_LDREX_STREX
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__ATOMIC_INLINE__ int32_t
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__bionic_swap(int32_t new_value, volatile int32_t* ptr)
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{
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int32_t prev, status;
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do {
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__asm__ __volatile__ (
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__ATOMIC_SWITCH_TO_ARM
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"ldrex %0, [%3]\n"
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"strex %1, %4, [%3]"
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__ATOMIC_SWITCH_TO_THUMB
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: "=&r" (prev), "=&r" (status), "+m" (*ptr)
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: "r" (ptr), "r" (new_value)
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: __ATOMIC_CLOBBERS "cc");
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} while (__builtin_expect(status != 0, 0));
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return prev;
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}
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#else /* !__ARM_HAVE_LDREX_STREX */
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__ATOMIC_INLINE__ int32_t
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__bionic_swap(int32_t new_value, volatile int32_t* ptr)
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{
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int32_t prev;
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/* NOTE: SWP is available in Thumb-1 too */
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__asm__ __volatile__ ("swp %0, %2, [%3]"
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: "=&r" (prev), "+m" (*ptr)
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: "r" (new_value), "r" (ptr)
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: "cc");
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return prev;
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}
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#endif /* !__ARM_HAVE_LDREX_STREX */
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/* Atomic increment - without any barriers
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* This returns the old value
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*/
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#ifdef __ARM_HAVE_LDREX_STREX
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__ATOMIC_INLINE__ int32_t
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__bionic_atomic_inc(volatile int32_t* ptr)
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{
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int32_t prev, tmp, status;
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do {
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__asm__ __volatile__ (
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__ATOMIC_SWITCH_TO_ARM
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"ldrex %0, [%4]\n"
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"add %1, %0, #1\n"
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"strex %2, %1, [%4]"
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__ATOMIC_SWITCH_TO_THUMB
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: "=&r" (prev), "=&r" (tmp), "=&r" (status), "+m"(*ptr)
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: "r" (ptr)
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: __ATOMIC_CLOBBERS "cc");
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} while (__builtin_expect(status != 0, 0));
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return prev;
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}
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#else
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__ATOMIC_INLINE__ int32_t
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__bionic_atomic_inc(volatile int32_t* ptr)
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{
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int32_t prev, status;
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do {
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prev = *ptr;
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status = __kernel_cmpxchg(prev, prev+1, ptr);
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} while (__builtin_expect(status != 0, 0));
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return prev;
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}
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#endif
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/* Atomic decrement - without any barriers
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* This returns the old value.
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*/
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#ifdef __ARM_HAVE_LDREX_STREX
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__ATOMIC_INLINE__ int32_t
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__bionic_atomic_dec(volatile int32_t* ptr)
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{
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int32_t prev, tmp, status;
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do {
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__asm__ __volatile__ (
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__ATOMIC_SWITCH_TO_ARM
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"ldrex %0, [%4]\n"
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"sub %1, %0, #1\n"
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"strex %2, %1, [%4]"
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__ATOMIC_SWITCH_TO_THUMB
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: "=&r" (prev), "=&r" (tmp), "=&r" (status), "+m"(*ptr)
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: "r" (ptr)
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: __ATOMIC_CLOBBERS "cc");
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} while (__builtin_expect(status != 0, 0));
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return prev;
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}
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#else
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__ATOMIC_INLINE__ int32_t
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__bionic_atomic_dec(volatile int32_t* ptr)
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{
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int32_t prev, status;
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do {
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prev = *ptr;
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status = __kernel_cmpxchg(prev, prev-1, ptr);
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} while (__builtin_expect(status != 0, 0));
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return prev;
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}
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#endif
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#endif /* SYS_ATOMICS_ARM_H */
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