e31bfae2ba
We're going to modify the __atomic_xxx implementation to provide
full memory barriers, to avoid problems for NDK machine code that
link to these functions.
First step is to remove their usage from our platform code.
We now use inlined versions of the same functions for a slight
performance boost.
+ remove obsolete atomics_x86.c (was never compiled)
NOTE: This improvement was benchmarked on various devices.
Comparing a pthread mutex lock + atomic increment + unlock
we get:
- ARMv7 emulator, running on a 2.4 GHz Xeon:
before: 396 ns after: 288 ns
- x86 emulator in KVM mode on same machine:
before: 27 ns after: 27 ns
- Google Nexus S, in ARMv7 mode (single-core):
before: 82 ns after: 76 ns
- Motorola Xoom, in ARMv7 mode (multi-core):
before: 121 ns after: 120 ns
The code has also been rebuilt in ARMv5TE mode for correctness.
Change-Id: Ic1dc72b173d59b2e7af901dd70d6a72fb2f64b17
89 lines
2.7 KiB
C
89 lines
2.7 KiB
C
/*
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* Copyright (C) 2011 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef BIONIC_ATOMIC_X86_H
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#define BIONIC_ATOMIC_X86_H
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/* Define a full memory barrier, this is only needed if we build the
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* platform for a multi-core device.
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*/
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#if defined(ANDROID_SMP) && ANDROID_SMP == 1
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__ATOMIC_INLINE__ void
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__bionic_memory_barrier()
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{
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__asm__ __volatile__ ( "mfence" : : : "memory" );
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}
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#else
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__ATOMIC_INLINE__ void
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__bionic_memory_barrier()
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{
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/* A simple compiler barrier */
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__asm__ __volatile__ ( "" : : : "memory" );
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}
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#endif
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/* Compare-and-swap, without any explicit barriers. Note that this function
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* returns 0 on success, and 1 on failure. The opposite convention is typically
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* used on other platforms.
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*/
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__ATOMIC_INLINE__ int
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__bionic_cmpxchg(int32_t old_value, int32_t new_value, volatile int32_t* ptr)
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{
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int32_t prev;
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__asm__ __volatile__ ("lock; cmpxchgl %1, %2"
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: "=a" (prev)
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: "q" (new_value), "m" (*ptr), "0" (old_value)
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: "memory");
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return prev != old_value;
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}
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/* Swap, without any explicit barriers */
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__ATOMIC_INLINE__ int32_t
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__bionic_swap(int32_t new_value, volatile int32_t *ptr)
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{
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__asm__ __volatile__ ("xchgl %1, %0"
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: "=r" (new_value)
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: "m" (*ptr), "0" (new_value)
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: "memory");
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return new_value;
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}
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/* Atomic increment, without explicit barriers */
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__ATOMIC_INLINE__ int32_t
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__bionic_atomic_inc(volatile int32_t *ptr)
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{
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int increment = 1;
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__asm__ __volatile__ ("lock; xaddl %0, %1"
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: "+r" (increment), "+m" (*ptr)
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: : "memory");
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/* increment now holds the old value of *ptr */
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return increment;
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}
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/* Atomic decrement, without explicit barriers */
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__ATOMIC_INLINE__ int32_t
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__bionic_atomic_dec(volatile int32_t *ptr)
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{
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int increment = -1;
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__asm__ __volatile__ ("lock; xaddl %0, %1"
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: "+r" (increment), "+m" (*ptr)
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: : "memory");
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/* increment now holds the old value of *ptr */
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return increment;
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}
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#endif /* BIONIC_ATOMIC_X86_H */
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