Duane Sand dd37251c47 [MIPSR6] setjmp supports mips32r6 and FP64A/FPXX reg models
Save and restore floating point registers via 64-bit
load/stores when possible.  Use assembler's builtin macro
ops to generate pairs of 32-bit load/stores on Mips I cpus.

Some cpus or FR modes have only 16 even-numbered dp fp regs.
This is exposed by _MIPS_FPSET, defined by existing compilers.

Change-Id: I7f617a3ffea8da41c402ef3a68ab32c91d3d7622
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