Duane Sand cd54195262 [MIPSR6] Use C-coded string ops on mips32r6/mips64r6 ...

The existing assembler code uses deprecated lwl/lwr/swl/swr ops.
Replacing those with misalignment-forgiving lw/sw ops may
involve careful performance tuning.

(cherry picked from commit bc5a3ec6df66d2456667ddf1d6dfaf623552169d)

Change-Id: I35167da27f2d406339b7f24b4a1fb270c87bc12e

2014-07-30 15:17:12 -07:00

..

bionic

[MIPSR6] setjmp supports mips32r6 and FP64A/FPXX reg models

2014-07-23 21:04:20 -07:00

include/machine

Clean up <machine/ieee.h>.

2014-04-16 16:31:17 -07:00

string

Unify our assembler macros.

2014-02-20 13:51:26 -08:00

syscalls

Add splice, tee, and vmsplice.

2014-06-24 19:03:31 -07:00

mips.mk

[MIPSR6] Use C-coded string ops on mips32r6/mips64r6

2014-07-30 15:17:12 -07:00