a147a1da5c
This patch fixes the ARM64 ABI for libm. fenv_t is now split in 32bit status and 32bit control. This mirrors the AArch64 FPU control and status registers (FPCR, FPSR). The patch also refactors the libm implementation for ARM64 into a finer grained control over the FPU registers. Bionic-benchmarks has been expanded with 3 more benchmarks for floating point operations. The new libm implementation for ARM64 performs better over all the math benchmarks available. Change-Id: I2a7f81d6b4e55c91f8a63a4c69614fc8b1bcf2db Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
103 lines
4.2 KiB
C
103 lines
4.2 KiB
C
/*-
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* Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD: src/lib/msun/arm/fenv.h,v 1.5 2005/03/16 19:03:45 das Exp $
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*/
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/*
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* In ARMv8, AArch64 state, floating-point operation is controlled by:
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*
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* * FPCR - 32Bit Floating-Point Control Register:
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* * [31:27] - Reserved, Res0;
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* * [26] - AHP, Alternative half-precision control bit;
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* * [25] - DN, Default NaN mode control bit;
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* * [24] - FZ, Flush-to-zero mode control bit;
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* * [23:22] - RMode, Rounding Mode control field:
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* * 00 - Round to Nearest (RN) mode;
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* * 01 - Round towards Plus Infinity (RP) mode;
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* * 10 - Round towards Minus Infinity (RM) mode;
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* * 11 - Round towards Zero (RZ) mode.
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* * [21:20] - Stride, ignored during AArch64 execution;
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* * [19] - Reserved, Res0;
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* * [18:16] - Len, ignored during AArch64 execution;
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* * [15] - IDE, Input Denormal exception trap;
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* * [14:13] - Reserved, Res0;
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* * [12] - IXE, Inexact exception trap;
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* * [11] - UFE, Underflow exception trap;
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* * [10] - OFE, Overflow exception trap;
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* * [9] - DZE, Division by Zero exception;
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* * [8] - IOE, Invalid Operation exception;
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* * [7:0] - Reserved, Res0.
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*
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* * FPSR - 32Bit Floating-Point Status Register:
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* * [31] - N, Negative condition flag for AArch32 (AArch64 sets PSTATE.N);
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* * [30] - Z, Zero condition flag for AArch32 (AArch64 sets PSTATE.Z);
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* * [29] - C, Carry conditon flag for AArch32 (AArch64 sets PSTATE.C);
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* * [28] - V, Overflow conditon flag for AArch32 (AArch64 sets PSTATE.V);
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* * [27] - QC, Cumulative saturation bit, Advanced SIMD only;
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* * [26:8] - Reserved, Res0;
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* * [7] - IDC, Input Denormal cumulative exception;
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* * [6:5] - Reserved, Res0;
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* * [4] - IXC, Inexact cumulative exception;
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* * [3] - UFC, Underflow cumulative exception;
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* * [2] - OFC, Overflow cumulative exception;
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* * [1] - DZC, Division by Zero cumulative exception;
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* * [0] - IOC, Invalid Operation cumulative exception.
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*/
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#ifndef _ARM64_FENV_H_
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#define _ARM64_FENV_H_
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#include <sys/types.h>
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__BEGIN_DECLS
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typedef struct {
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__uint32_t __control; /* FPCR, Floating-point Control Register */
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__uint32_t __status; /* FPSR, Floating-point Status Register */
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} fenv_t;
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typedef __uint32_t fexcept_t;
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/* Exception flags. */
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#define FE_INVALID 0x01
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#define FE_DIVBYZERO 0x02
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#define FE_OVERFLOW 0x04
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#define FE_UNDERFLOW 0x08
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#define FE_INEXACT 0x10
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#define FE_DENORMAL 0x80
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#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \
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FE_OVERFLOW | FE_UNDERFLOW | FE_DENORMAL)
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/* Rounding modes. */
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#define FE_TONEAREST 0x0
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#define FE_UPWARD 0x1
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#define FE_DOWNWARD 0x2
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#define FE_TOWARDZERO 0x3
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__END_DECLS
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#endif /* !_ARM64_FENV_H_ */
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