82fa43febc
libc/kernel/tools/update_all.py script. This patch ignores any changes to libc/kernel directory not related to MIPS architecture. Change-Id: I2c9e461dccb7c33eb4420be2db1a562f45137c8d Signed-off-by: Raghu Gandham <raghu@mips.com> Signed-off-by: Chris Dearman <chris@mips.com>
187 lines
7.6 KiB
C
187 lines
7.6 KiB
C
/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef __ASM_CPU_FEATURES_H
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#define __ASM_CPU_FEATURES_H
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#include <asm/cpu.h>
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#include <asm/cpu-info.h>
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#include <cpu-feature-overrides.h>
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#ifndef current_cpu_type
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#define current_cpu_type() current_cpu_data.cputype
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#endif
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#ifndef cpu_has_tlb
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#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
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#endif
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#ifndef cpu_has_4kex
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
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#endif
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#ifndef cpu_has_3k_cache
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#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#endif
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#define cpu_has_6k_cache 0
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#define cpu_has_8k_cache 0
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#ifndef cpu_has_4k_cache
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
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#endif
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#ifndef cpu_has_tx39_cache
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#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#endif
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#ifndef cpu_has_fpu
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#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
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#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#else
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#define raw_cpu_has_fpu cpu_has_fpu
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#endif
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#ifndef cpu_has_32fpr
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
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#endif
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#ifndef cpu_has_counter
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#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#endif
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#ifndef cpu_has_watch
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#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
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#endif
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#ifndef cpu_has_divec
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#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
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#endif
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#ifndef cpu_has_vce
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
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#endif
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#ifndef cpu_has_cache_cdex_p
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#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#endif
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#ifndef cpu_has_cache_cdex_s
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#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
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#endif
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#ifndef cpu_has_prefetch
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#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
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#endif
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#ifndef cpu_has_mcheck
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
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#endif
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#ifndef cpu_has_ejtag
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#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#endif
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#ifndef cpu_has_llsc
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#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
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#endif
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#ifndef cpu_has_mips16
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#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
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#endif
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#ifndef cpu_has_mdmx
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
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#endif
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#ifndef cpu_has_mips3d
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#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#endif
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#ifndef cpu_has_smartmips
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#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
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#endif
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#ifndef cpu_has_vtag_icache
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#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
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#endif
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#ifndef cpu_has_dc_aliases
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
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#endif
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#ifndef cpu_has_ic_fills_f_dc
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#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#endif
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#ifndef cpu_has_pindexed_dcache
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#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
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#endif
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#ifndef cpu_icache_snoops_remote_store
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#define cpu_icache_snoops_remote_store 1
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#endif
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#ifndef cpu_has_mips32r1
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
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#endif
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#ifndef cpu_has_mips32r2
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#define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#endif
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#ifndef cpu_has_mips64r1
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#define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
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#endif
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#ifndef cpu_has_mips64r2
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#define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
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#endif
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#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2)
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#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
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#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
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#ifndef cpu_has_dsp
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
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#endif
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#ifndef cpu_has_mipsmt
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#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#endif
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#ifndef cpu_has_userlocal
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#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
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#endif
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#ifndef cpu_has_vint
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#define cpu_has_vint 0
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#endif
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#ifndef cpu_has_veic
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define cpu_has_veic 0
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#endif
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#ifndef cpu_has_inclusive_pcaches
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#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#endif
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#ifndef cpu_dcache_line_size
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#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
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#endif
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#ifndef cpu_icache_line_size
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#define cpu_icache_line_size() cpu_data[0].icache.linesz
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#endif
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#ifndef cpu_scache_line_size
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define cpu_scache_line_size() cpu_data[0].scache.linesz
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#endif
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#endif
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